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Explorer
Explorer
3,586 Views
Registered: ‎11-06-2011

TestBeanching User Logic

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Hey.

 

I've created an IPIF, imported it to ISE, change it and now I try to test Bench it.

 

This is what I get

 

http://imageshack.us/photo/my-images/808/27648496.png/

 

Now, I can set the test bench my self, but is there any reason for this error I'm getting?

 

Thanks a lot.

 

Assaf.

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Explorer
Explorer
4,403 Views
Registered: ‎11-06-2011

Re: TestBeanching User Logic

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Hey.

 

Do u mean this window?

 

http://imageshack.us/photo/my-images/12/33743353.png/

 

Anyway, I didn't give you all the information...

 

In the user logic there is the following sentences

 

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

 

I open a new project with only the User_Logic.vhd file, added the Library manual and it worked.

 

Thank you very much.

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Teacher
Teacher
3,583 Views
Registered: ‎08-14-2007

Re: TestBeanching User Logic

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Hi,

you just got the bare testbench template without the automatic instantiation of your DUT, therefore there are still unresolved tags that are not intended to stay in the testbench, thus causing VHDL syntax errors.

 

When you create a testbench with the "New Source Wizard" a dialog box asks you for a module to be used in that testbench.

If none is chosen you might end up with this.

Just delete this bare template and repeat the "New Source Wizard".

 

Have a nice simulation

  Eilert

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Explorer
Explorer
4,404 Views
Registered: ‎11-06-2011

Re: TestBeanching User Logic

Jump to solution

Hey.

 

Do u mean this window?

 

http://imageshack.us/photo/my-images/12/33743353.png/

 

Anyway, I didn't give you all the information...

 

In the user logic there is the following sentences

 

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

 

I open a new project with only the User_Logic.vhd file, added the Library manual and it worked.

 

Thank you very much.

View solution in original post

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