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Visitor adrianjgp
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4,493 Views
Registered: ‎04-26-2012

Time performance analysis

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Hello, everyone.

I shouldn't do this question, but I'm doubtful about how to analyze the timing of a segmented module I'm designing. I'm an Engineering student and in my last courses I worked with Altera FPGAs and Quartus, but I've been recently working with Xilinx FPGAs.

In the Altera's Quartus software, I used a tool called "TimeQuest Alalyzer" to find the maximum work frequency of my project (I understand this frequency is obtained from the largest critical route from every input to every output).

Of course, in ISE there is also a Timing Analyzer tool. In my project navigator, I run the process up to the "Generate Post-Map Static Timing", what generates a .twx file, but I'm not sure what time I must see. On the "Data sheet" report there is a large list of time values. From all those generates values, which one is the closest time to the performance indicator I'm looking for (the highest possible frequency of the whole system)?

 

Thank you in advance.

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Historian
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Registered: ‎02-25-2008

Re: Time performance analysis

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Anyways -- to see if your design meets your constraints, after the place and route finishes, do the "Generate Post-Place & Route Static Timing" from the Project Navigator, and choose "Analyze Post-Place & Route Static Timing." You'l get a list of the constraints, indications as to whether they meet the constraints, and lists of the slowest paths for each constraint.

 

Now in the Process Properties for "Generate Post Place & Route Static Timing," there's an option called "Perform Advanced Analysis." when run with this option, the analyzer ignores your constraints and tells you how fast each clock path in the design can run. it also tells you the delays through purely combinatorial paths. BUT -- if you've run the place and route without supplying timing constraints, this option still won't tell you potentially how fast the design will go, because again, the place and route didn't work too hard to meet any particular timing requirement, so the results may have long paths and such.

----------------------------Yes, I do this for a living.

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Historian
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Registered: ‎02-25-2008

Re: Time performance analysis

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@adrianjgp wrote:

Hello, everyone.

I shouldn't do this question, but I'm doubtful about how to analyze the timing of a segmented module I'm designing. I'm an Engineering student and in my last courses I worked with Altera FPGAs and Quartus, but I've been recently working with Xilinx FPGAs.

In the Altera's Quartus software, I used a tool called "TimeQuest Alalyzer" to find the maximum work frequency of my project (I understand this frequency is obtained from the largest critical route from every input to every output).

Of course, in ISE there is also a Timing Analyzer tool. In my project navigator, I run the process up to the "Generate Post-Map Static Timing", what generates a .twx file, but I'm not sure what time I must see. On the "Data sheet" report there is a large list of time values. From all those generates values, which one is the closest time to the performance indicator I'm looking for (the highest possible frequency of the whole system)?

 

Thank you in advance.


I suppose the first question to ask is: are you using timing constraints or not?

 

Because if you're not, then the tools won't make any special effort to make the design run fast. So you'll get what you get.

 

If you do use timing constraints, then the tools will work to ensure that the design meets them. It won't do any more work; in other words, if you constrain a clock domain for 100 MHz operation, the tools won't try to make the design work at 200 MHz.

 

Most rational designs have clock-speed requirements so throwing darts at it to see if it goes faster doesn't buy you anything.

----------------------------Yes, I do this for a living.
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Historian
Historian
5,889 Views
Registered: ‎02-25-2008

Re: Time performance analysis

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Anyways -- to see if your design meets your constraints, after the place and route finishes, do the "Generate Post-Place & Route Static Timing" from the Project Navigator, and choose "Analyze Post-Place & Route Static Timing." You'l get a list of the constraints, indications as to whether they meet the constraints, and lists of the slowest paths for each constraint.

 

Now in the Process Properties for "Generate Post Place & Route Static Timing," there's an option called "Perform Advanced Analysis." when run with this option, the analyzer ignores your constraints and tells you how fast each clock path in the design can run. it also tells you the delays through purely combinatorial paths. BUT -- if you've run the place and route without supplying timing constraints, this option still won't tell you potentially how fast the design will go, because again, the place and route didn't work too hard to meet any particular timing requirement, so the results may have long paths and such.

----------------------------Yes, I do this for a living.

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