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Observer
Observer
7,456 Views
Registered: ‎11-23-2010

Timing constraint impossible to meet issue ...

Hi

 

I was implementing a design on Virtex5 FPGA and in the implementation/map stage, I ran into this error - 

 

Pack:1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the constraint. A timing constraint summary
below shows the failing constraints (preceded with an Asterisk (*)). Please
use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
PCF files to identify which constraints and paths are failing because of the
component delays alone. If the failing path(s) is mapped to Xilinx components
as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing
the path. To allow the tools to bypass this error, set the environment
variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.

 

I am new to such timing issues so my questions are - 

1) If I do use the env variable mentioned above and am able to bypass the error, is that recommended or can I run into more issues?

2) The map report says that signals of a particular fifo that I have are giving this problem. How can I trace the exact cause of this issue?  

3) I was slowly adding modules into my design, and after adding some new modules, this error showed up ... so what would this indicate?

4) What would be a good fix for such an issue, and the approach?

 

I've also attached the timing report. Any light on this issue will be of great help to me ...

 

Thanks and regards,

Zubin Kumar.

 

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6 Replies
Professor
Professor
7,451 Views
Registered: ‎08-14-2007

You will not fix the problem by setting the environment variable, however you will allow Map

to complete so you can get a complete timing report that shows the failing paths.  Without

that there is no way to debug the issue.

 

It is possible that you have too many levels of logic for your required clock period, or you

have some clock crossings that are being unnecesssarily constrained by the tools.  Without

at least a post-map timing report you don't know which is the case.

 

Bottoms line, set the variable, let map complete and look at the post map report to find

the failing path(s).  Then decide whether you need to fix the paths or add constraints to

ignore them.

 

-- Gabor

-- Gabor
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Observer
Observer
7,441 Views
Registered: ‎11-23-2010

Hi,

 

Thanks for the reply. Where do I need to go to set this env variable so that I can complete the map and P&R?

 

Thanks and regards,

Z.

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Instructor
Instructor
7,436 Views
Registered: ‎07-21-2009

Where do I need to go to set this env variable so that I can complete the map and P&R?

 

How to do this depends on the operating system.

Why not search the web for this information?  Would you like help with the search?

 

With the more recent versions of ISE, the Navigator GUI does not depend on environment variables.

Are you ready to update your ancient ISE 10.1 to a newer version?

 

-- Bob Elkind

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Professor
Professor
7,414 Views
Registered: ‎08-14-2007

If you're using WIndows, I'd suggest downloading the Rapid Environment Editor:

 

http://www.rapidee.com/en/history

 

This makes it much easier to manage your environment variables.

 

-- Gabor

-- Gabor
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Observer
Observer
7,410 Views
Registered: ‎11-23-2010

hi,

 

thanks for the replies, i was able to set the env variable and make the bitfile. the bitfile looks to run properly, but in the design summary, i have 2 failing constraints. i have attached the report to the post (timing_report.jpg). 

 

the first 2 constraints are not being met. I am not sure if the report indicates a setup or hold time failure. and if it is either, how can i resolve them? should i just remove the constraint?

 

any inputs for this will be of great help to me.

 

thanks.

z.

timing_report.JPG
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Professor
Professor
7,405 Views
Registered: ‎08-14-2007

You need to create a Verbose timing report to see the individually failing paths and decide

whether these are actually problems or not.

 

The two constraints that fail are both setup issues (negative slack is only on the SETUP line).

They also appear to be PERIOD constraints, but that doesn't necessarily mean that the failing

paths don't cross clock domains.  You need to look at the failing paths in the report viewer,

which will show source and destination clocks.

 

If the paths are crossing clock domains that you consider to be unrelated (even though they

may be generated from the same clock input via DCM or PLL), then you may be able to ignore

them.

 

If the paths are on the same clock for source and destination, then you need to check if these

paths can safely take more than one clock period to propagate, and if so create multicycle

"FROM : TO" constraints for them.

 

If none of these are the case, then you need to look closely at the design and decude how to

help it run faster.  Search the forums for "timing closure" to help with this sort of issue.

 

-- Gabor

-- Gabor
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