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Explorer
Explorer
12,395 Views
Registered: ‎08-30-2007

Timing differences when Chipscope is used

Hello


I have a question for you, something that troubles me a long time now and I want your opinion.


I’ve noticed that when I insert a Chipscope core in an ISE or EDK project (using the same constraints) the timing score is always better than it is without Chipscope, for a time-problematic design, or correspondingly, if the timing score reaches 0 the effort of the tool is much smaller.

I understand that when I use Chipscope there are many changes and new paths but I can not explain the timing improvement. My best guess is that when I insert Chipscope the tool automatically generates some new constraints that help the whole process or maybe some buffers are added that change the timing.


So, I would be very glad if someone can solve this puzzle for me and I also have another relevant question. Is there a way of extracting information (e.g. constraints) from the project with the Chipscope core so as to use them at the original design and improve its timing?

Thanks in advance for your help

George


p.s. I think that this thread has immediate relation to the “General Discussion/Implementation problems” thread

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3 Replies
Contributor
Contributor
12,356 Views
Registered: ‎07-31-2007

Re: Timing differences when Chipscope is used

George,
       You are correct this is very similar to the Implementation problems thread.    In any case, Chipscope will only add constraints if the option is turned on in Chipscope (which it is by default), and those constraints only affect the Chipscope paths, they will not cover the rest of your design.  The fact that the timing scores improve must be conincidence because there is no reason that the tools would spit out a better result with Chipscope in the design.  This all leads me to the same place as the other thread...
 
The first thing that jumps out at me is timing.  I would look at several different things to find out more.
 
A.  Run Timing Analyzer with both designs, and generate/compare timing reports for the constraints that you have in the UCF.
B.  Run Timing Analyzer with both designs, and generate/compare timing reports for Auto Generated constraints ( Analyze - Analyze Against Auto Generated Constraints)
 
I would recommend narrowning the timing differences into 3 areas, which match up with the 3 types of consrtaints that every design should have.
 
1.  Input timing - OFFSET IN Constraints are used to control this
2.  Internal timing - PERIOD Constraints are used to control this
3.  Output timing - OFFSET OUT Constraints are used to control this
 
You will see that when you run Test B from above that the tools will spit out constraints for 1,2 and 3.   They are a good baseline for how quickly your design can run.... take those baselines from the w/Chipscope design, then apply them to the original design.  This will get you going in the right direction,
 
-Three.Jax
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Explorer
Explorer
12,297 Views
Registered: ‎08-30-2007

Re: Timing differences when Chipscope is used


Hello again and thank you very much for your reply.

First of all I want to say that I don’t think that the timing improvement is a coincidence. I’ve noticed that this behavior is almost the rule and not something occasional.  Many designs seem to have the same behavior and some of my colleagues have noticed the same thing.

I’ve tried to use your method and surely the auto generated constraints are different between the two versions. After that I wanted to apply the constraints of the w/Chipscope project to the other one but I've had some problems.

The only constraint that I'm able to apply is the “Internal timing” and for some reason the timing is getting worse. Maybe I can explain that but my biggest problem is that I can not apply the other two constraints. The reason is that the UCF "commands" OFFSET IN and OFFSET OUT can only be used with externally generated clocks and not with internal ones. Of course, Timing Analyzer generates the constraints for the internal clocks of the design.

Can you please tell what can I do so as to apply the other two constraints?



Thank you again



George



Message Edited by gtze on 09-24-2007 03:15 PM
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Contributor
Contributor
12,238 Views
Registered: ‎07-31-2007

Re: Timing differences when Chipscope is used

George,
       I guess there was part of my thought that was omitted when I wrote the previous message.  The Auto Generated constraints will give you a baseline to compare the 2 designs, but you will need to be careful in applying the constraints to the w/o chipscope design.  All constraints are made up of 2 parts. 
 
1.  The Timegroup
2.  The requirement
 
While the Auto-gen constraints from the w/chipscope design will provide the an idea of what the requirement should be, the Timegroup is where you may trip up.  Timegroups are the groups of BELs (Basic Elements) that can be used in a constraint.  The design w/chipscope may have different BELs than the original design, given that they are in fact 2 different designs.  To revise my suggestions from before, use the requirements from the Auto-gen Reported constraints, and not the timegroups.
 
-Three.jax
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