09-20-2007 06:13 AM
I have a question for you, something that troubles me a long time now and I want your opinion.
I’ve noticed that when I insert a Chipscope core in an ISE or EDK project (using the same constraints) the timing score is always better than it is without Chipscope, for a time-problematic design, or correspondingly, if the timing score reaches 0 the effort of the tool is much smaller.
I understand that when I use Chipscope there
are many changes and new paths but I can not explain the timing improvement. My
best guess is that when I insert Chipscope the tool automatically generates
some new constraints that help the whole process or maybe some buffers are added
that change the timing.
So, I would be very glad if someone can solve this puzzle for me and I also have another relevant question. Is there a way of extracting information (e.g. constraints) from the project with the Chipscope core so as to use them at the original design and improve its timing?
Thanks in advance for your help
p.s. I think that this thread has immediate relation to the “General Discussion/Implementation problems” thread
09-20-2007 08:12 AM
09-24-2007 05:12 AM - edited 09-24-2007 05:15 AM
09-27-2007 01:16 PM