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4,316 Views
Registered: ‎06-05-2013

Tool encounters 10240 load/store instructions to analyze which may result in long runtime

Hi~

   HLS says " Tool encounters 10240 load/store instructions to analyze which may result in long runtime." And there's a long runtime.

   What can I do then?

   Thank!

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Historian
Historian
4,306 Views
Registered: ‎02-25-2008


@smileworker2012 wrote:

Hi~

   HLS says " Tool encounters 10240 load/store instructions to analyze which may result in long runtime." And there's a long runtime.

   What can I do then?

   Thank!


Reduce the number of load/store operations?

Stop pretending that HLS is a viable FPGA design tool?

----------------------------Yes, I do this for a living.
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Newbie
Newbie
2,624 Views
Registered: ‎05-25-2016


@bassman59 wrote:

@smileworker2012 wrote:

Hi~

   HLS says " Tool encounters 10240 load/store instructions to analyze which may result in long runtime." And there's a long runtime.

   What can I do then?

   Thank!


Reduce the number of load/store operations?

Stop pretending that HLS is a viable FPGA design tool?


 

 

"Reducing the number of load/store operations" is not possible, its not like There would be dummy load/store instructions present in the program which are there to make me happy and I can go ahead and remove them....

"pretending that HLS is a viable FPGA design tool", Is this supposed to be a help forum or what ? common. 

 

I am a masters student at the university of Florida and I am porting sysgtem verilog code of a very reputable organization into the vivado HLS platform. 

 

the following arrays are present in the top module:
static ap_uint <5>   array_a[5][9][128],
static ap_uint <12> array_b[5][9][6],
static ap_uint <4>   array_c[5][9][128]

 

these are initialized by the testbench via select signals before the top module uses them 

 

if(we)

{

  //write one of the static arrays based on a "switch(sel)" statement

}

else

{

   //everything else in the top module. 

}

 

thus there are stores and loads. these can not be reduced. 

Synthesis eats up my ram and my system freezes. (currently running on a 8 gb of ram, will test with more ram soon)

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Advisor
Advisor
2,610 Views
Registered: ‎04-26-2015

Hmm, I'm not sure why you'd port from Verilog to HLS. HLS will just convert it back to Verilog for you, and probably do a much worse job than what the original code managed.

 

 

Would you mind expanding the code example a bit? Are those arrays fully partitioned? If so, anything you can do to reduce the partitioning level will help a lot (huge multiplexers are expensive). Alternatively, have you got a huge unrolled loop that reads/writes from the arrays? That would have a similar effect.

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Highlighted
2,489 Views
Registered: ‎05-12-2016

Hi,

 

How long did it take for the synthesis to finish? I have 11065 load/store. I've been waiting for a couple of hours and starting to wonder how long this is going to take.

 

Best Regards,

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Visitor
Visitor
2,347 Views
Registered: ‎05-19-2016

Hi do you have any idea how long does it take? My design has around 12000 load/store too.

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