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Adventurer
Adventurer
2,639 Views
Registered: ‎09-16-2009

Top Level Module

Is there an advantage of programming your functions within a side file and call from your top level module in comparison to just having the functions in your top level design?  When I say advantage, is there a reduction in LUT used.

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Xilinx Employee
Xilinx Employee
2,628 Views
Registered: ‎01-03-2008

The  "functions" and "calling" terminology are primarily software concepts and not hardware concepts.  Both VHDL and Verilog have "function" constructs that are usually used to handle a simple equation or type conversion that may be used in many places throughout the design, but the use of these constructs is not very common.

 

In hardware design it is very desirable to have hierarchy in the design to be able to easily partion the logic in to functional blocks that are easier to understand and maintain.  In your top level design you would have multiple modules that would be instantiated and within each of the modules you may have other modules if the design needs to be futher broken down.  A common functional block  may be instantiated multiple in the same module level or within different modules as needed. 

 

The resulting logic and speed of the design with or without hierarchy should be the same, but there may be some area or speed optimizations that cannot be made across the hierarchical module boundaries if the boundaries are fixed.  Most synthesizers have an option to flatten the design to allow for maximum optimization across the module boundaries and hierarchy at the cost of increased runtime and memory.

------Have you tried typing your question into Google? If not you should before posting.
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