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mishra.pras
Participant
Participant
13,861 Views
Registered: ‎03-07-2011

Two dimensional array in VHDL

Dear users,

 

I want to implement a two dimensional array (memory) in VHDL, and want to access (read ) it through various components,  one of the components (both for reading and writing)is in verilog.

Can anyone suggest me a way to declare a module and its linkage to various components.

 

Pras

Pras
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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

It would be easier to stick to one HDL if at all possible.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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mishra.pras
Participant
Participant
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Registered: ‎03-07-2011

Ok.

But what is the procedure to access the memory (array) in the top file from other components?

Pras

Pras
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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

I'm not sure what you are actually trying to do and in what context.

In VHDL you cannot access signals inside other architectures except via their entity's ports. Verilog is not so strict.

Assuming VHDL, you need to design access structures to enable you to write and read the memory array. Or you could use LogiCore to build you a memory component that has the ports and usage thereof defined.

Have you done digital design before?

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"If it don't work in simulation, it won't work on the board."
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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

what is your experiance in vhdl ?

 

can you write a single vector module ?

 

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gszakacs
Instructor
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Registered: ‎08-14-2007

VHDL probably allows you to have two dimensional arrays in the component's ports.

Verilog does not allow multidimensional arrays in ports.

 

So the usual method is to define a two-dimensional array that behaves just like

distributed or block RAM (depending on how big it is and how it's used), possibly

multiported.  Then run the address and data ports (not the array itself) of the

RAM to the module ports.

 

It doesn't really matter whether the module containing the RAM is VHDL or Verilog.  The

important point is to have all of the behavioral code for memory access (the address

and data ports, and read and write processes) in the module where the memory

is defined.  You can get this from the language templates or the XST manual.

 

-- Gabor

-- Gabor
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mishra.pras
Participant
Participant
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Registered: ‎03-07-2011

Dear users, I am new to FPGAs. I have made some programs in verilog. VHDL I am trying for the first time. My concern is how can we bring the memory to entity port? That too has to be used as input (many components) and output(for one comp, for writing purpose). In verilog I was able to access the memory simply as reg1<=memory[address]; that too inside a single module. I am confused how to bring this memory at port, there may be too many wires to connect to diff modules/entity. Again I can go for declare as many vectors/reg as memory elements, but the problem is same how to bring them all at the port? Please provide me a direction. Pras
Pras
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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

If you have some experience in Verilog, why do you need/want to switch to VHDL? If you can do it in Verilog, do it in Verilog!

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"If it don't work in simulation, it won't work on the board."
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gszakacs
Instructor
Instructor
13,816 Views
Registered: ‎08-14-2007

 


@mishra.pras wrote:
Dear users, I am new to FPGAs. I have made some programs in verilog. VHDL I am trying for the first time. My concern is how can we bring the memory to entity port? That too has to be used as input (many components) and output(for one comp, for writing purpose). In verilog I was able to access the memory simply as reg1<=memory[address]; that too inside a single module. I am confused how to bring this memory at port, there may be too many wires to connect to diff modules/entity. Again I can go for declare as many vectors/reg as memory elements, but the problem is same how to bring them all at the port? Please provide me a direction. Pras

 

This is really a hardware design issue, not a language issue.  If you don't want synthesis to

generate thousands of flip-flops to build your "memory" you need to abide by the rules of the

available memory structures (single or dual port, distributed or block RAM).  The memory itself

should always be contained within one module (or component).  That module needs to have

all of the direct access to the memory array as in reg1<=memory[address];  The ports

of the module are the ports of the memory (addr_a, addr_b, din_a, din_b, dout_a, dout_b ...)

not the memory array itself.

 

As I said in the earlier post, you can find VHDL (or Verilog) templates for inference of

all available memory types in the language templates as well as the XST user manual.

 

So the short answer of how to attach the memory array to module (component) ports is

don't do it.  While it is allowed in VHDL, you can't access it from Verilog, and the synthesis

tools will not infer memory, but rather tons of flip-flops.

 

-- Gabor

-- Gabor
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mishra.pras
Participant
Participant
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Registered: ‎03-07-2011

Dear users,
I wrote a vhdl programme to write and read memory. I did it successfully.

Then I added this vhdl file as a component to another verilog program. I tried to acces theis vhdl component using address and data lines. But during synthesis it displayed error of multisourcing on the data signal. Though this data signal is output of the vhdl programme and is being used as an input only.

Is this problem due to the mixing of verilog and vhdl.
Pras
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drjohnsmith
Teacher
Teacher
5,655 Views
Registered: ‎07-09-2009

Hi

 

I'm going to be blunt here,

   sorry

 

you are way off base. way way off base.

 

don't mix languages, that is true, but that is not the basic feature,

    it's that you are not experianced enough in vhdl / verilog,

        and you seem to be approaching a description language in the same way

            you would a stack process like C++.

 

you need to take step back me thinks,

 

 

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mcgett
Xilinx Employee
Xilinx Employee
5,651 Views
Registered: ‎01-03-2008

> I wrote a vhdl programme to write and read memory. I did it successfully.

 

Actually, you created a VHDL design.  You are not creating "programs" you are creating a hardware design.

 

> Then I added this vhdl file as a component to another verilog program.

 

Actually, you added the VHDL design as a component or sub-module in another Verilog design.

 

> I tried to acces theis vhdl component using address and data lines.

 

You are creating hardware and not software, so you are not accessing the VHDL read/write memory design that you created earlier.  The Verilog design would be controlling the VHDL design by providing the necessary hardware signals for address, data and clock and in return using the data output in other parts of the Verilog design.

 

> But during synthesis it displayed error of multisourcing on the data signal. Though this data signal is

> output of the vhdl programme and is being used as an input only.

 

When the synthesizer reports that a net has multiple sources it means that you have two points in your HDL that are trying to change the state of the net.   You will need to re-examine your HDL source to determine where this occuring.

 

My guess is that this is occuring because you are trying to do something that is not practical in a real design.  Way back at the beginning of this thread you stated that you wanted to have a single two dimensional memory array that can be accessed from many places within the design.  This concept works with software running on a CPU, but you are not designing software you are designing hardware.  

 

The hardware that you are creating runs everything circuit at the same time time, while software runs each instruction sequentially.  If you have 10 modules that each want to read or write the memory array then that means that you need a 10 port memory.   Creating a 10 port memory is not practical in an FPGA, but can be done if needed.  You will need to create a memory module that has 10 ports each with address, data_in, data_out and read/write in order to do this. 

 

> Is this problem due to the mixing of verilog and vhdl.

 

No it is because your design is wrong.

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