cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
3,696 Views
Registered: ‎11-23-2013

Usage of Dynamic Phase Shift Interface in MMCM not clear

Jump to solution

Hello,

 

In the ug472, it says "Each CLKOUT and the CLKFBOUT divider can be individually selected for phase shifting. The attributes CLKOUT[0:6]_USE_FINE_PS and CLKFBOUT_USE_FINE_PS select the output clocks to be dynamically phase shifted. The dynamic phase-shift amount is common to all the output clocks selected."

 

And the dynamic phase shift interface includes PSEN, PSINCDEC, PSCLK, and PSDONE. If user set the attributes CLKOUT*_USE_FINE_PS of multiple output clocks to be TRUE, user cannot use PSEN, PSINCDEC, PSCLK, and PSDONE to specify which output clock should be shifted.

 

So, it seems that the dynamic phase shift interface will shift all the output clocks whose CLKOUT*_USE_FINE_PS set to TRUE at the same time.

Is that true??

 

BTW, I use the 7series FPGAs

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
4,644 Views
Registered: ‎07-11-2011

Hi,

 

Which version of UG472 are you referring?

I do not see the statement "user cannot use PSEN, PSINCDEC, PSCLK, and PSDONE to specify which output clock should be shifted" in  7 Series FPGAs Clocking Resources User Guide UG472 (v1.9) April 8, 2014, if you see it can you mention the page number so that we can cross check?

 

For your specific question it is true that the dynamic phase shift interface will shift all the output clocks whose CLKOUT*_USE_FINE_PS set to TRUE at the same time.

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
4,645 Views
Registered: ‎07-11-2011

Hi,

 

Which version of UG472 are you referring?

I do not see the statement "user cannot use PSEN, PSINCDEC, PSCLK, and PSDONE to specify which output clock should be shifted" in  7 Series FPGAs Clocking Resources User Guide UG472 (v1.9) April 8, 2014, if you see it can you mention the page number so that we can cross check?

 

For your specific question it is true that the dynamic phase shift interface will shift all the output clocks whose CLKOUT*_USE_FINE_PS set to TRUE at the same time.

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
Highlighted
Explorer
Explorer
3,656 Views
Registered: ‎11-23-2013
Thanks for your answer.

"user cannot use PSEN, PSINCDEC, PSCLK, and PSDONE to specify which output clock should be shifted" was just my understanding of the ug472. I should write my word more clear.

Thank you.
0 Kudos