I've been using Vivado for more than a year now. All in all, it is a good product. It adds in SystemVerilog support, gives us much better layout and timing tools, and is very stable. I can't recall whether I've ever had a Vivado crash. But it's not all perfect. There are plenty of small UI and UX design flaws. I have been in touch with Xilinx on many of them, but I can't make any headway.
Has anyone else felt this way?
Here are a few that I have tried to get a response on:
1. Focus stealing in Linux. Vivado constantly steals focus from my editor. -- No response or work on this from Xilinx.
2. Create IP that I immediately need to modify - no synthesis run available until after I generate first time. So I must create, generate, then change to unmanaged, modify, and then generate again. -- No response again
3. Generate Bitstream doesn't detect that it is up to date - just starts running again.. And of course erases the already created bitstream. -- No response
4. After burning a SPI Flash, the default in the Program dialog is changed to: /opt/Xilinx/vivado/2015.3/data/xicom/cfgmem/spi_xc7vx75t_pullnone.bit
-- Insists that this is intentional. But why?
All of these issues have been reported since before 2015.1 came out.