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Voyager
Voyager
11,557 Views
Registered: ‎02-10-2012

Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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Hey every one,


Quick technical question :

 

I have been reading a bit about synchronous design practices and trying to implement those ideas in my design. I wanted to know if its a good design practice to drive the CE pin of the flip flops using clock signals ?

 

The situation is as follows : I have a master clock from the MMCM that runs throght the device via a BUFG. My final aim is to make every design module synchronous to this clock. I need to drive some of the read and write enable lines of FIFO's and general logic FF's at a dynamic divided frequency when compared to the master clock. My idea was to implement a dynamic divider circuit that generates my divided clock and then route them to my logic via a BUFG so that they get the least possible skew.

 

My question is : Can I use the clock signal coming from a BUFG to drive CE pins of FF's and Enable lines of FIFOS's ? This way everything is synchronous to my master clock.

 

I am using ISE 14.7 and working on a design targetting Zynq 7020 .

 

Cheers

Arvind

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1 Solution

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Historian
Historian
20,249 Views
Registered: ‎02-25-2008

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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@arvindnr wrote:

Hey every one,


Quick technical question :

 

I have been reading a bit about synchronous design practices and trying to implement those ideas in my design. I wanted to know if its a good design practice to drive the CE pin of the flip flops using clock signals ?


No, because the global clock nets go only to clock loads and not to a flip-flop's CE pin. You'll get a routing error.

 

You can, however, use logic to drive a BUFG's CE input, so that the clock from that BUFG going to its loads will be enabled as you desire.

----------------------------Yes, I do this for a living.

View solution in original post

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7 Replies
Historian
Historian
20,250 Views
Registered: ‎02-25-2008

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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@arvindnr wrote:

Hey every one,


Quick technical question :

 

I have been reading a bit about synchronous design practices and trying to implement those ideas in my design. I wanted to know if its a good design practice to drive the CE pin of the flip flops using clock signals ?


No, because the global clock nets go only to clock loads and not to a flip-flop's CE pin. You'll get a routing error.

 

You can, however, use logic to drive a BUFG's CE input, so that the clock from that BUFG going to its loads will be enabled as you desire.

----------------------------Yes, I do this for a living.

View solution in original post

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Voyager
Voyager
11,488 Views
Registered: ‎02-10-2012

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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Hey,

 

Thanks for your input. Your method seems to be more eligant and simple :) I will give it a try.


Cheers

Arvind

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Xilinx Employee
Xilinx Employee
11,475 Views
Registered: ‎10-11-2007

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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Just to clarify. There are limited resources in the interconnect that allow inputs from the global clock tree to a CLB including CE and RST. But you only get two of those and if you have a constant 0 going to the CLB then one of the two is used.

 

Other than that, timing would be challenging in you scenario. Much better to use the CE on the BUFGCE.

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Voyager
Voyager
11,456 Views
Registered: ‎02-10-2012

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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Thanks for your reply Ralfk,

 

I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic. 

 

I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :

 

1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.

 

2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.

 

If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.

 

Since I am still in my modular VHDL design phase I can't test my theory yet.

 

Any inputs ?

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Historian
Historian
11,443 Views
Registered: ‎02-25-2008

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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@arvindnr wrote:

Thanks for your reply Ralfk,

 

I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic.

 

I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :

 

1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.

 

2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.


I'm not sure I understand why you're trying to do this. Is it a matter of not meeting timing?

 

Why not just control the RD and WR signals as necessary, running them off the RCLK and the WCLK respectively? 


If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.


The FIFO clocks need not be continuous, but it helps. It makes timing analysis simpler and since the flags are dependent on the clock then if the clock stops you might not see a flag change. Tying RD true and manipulating the read clock frequency sounds a lot more difficult than asserting the RD flag when a read is necessary.

 

Can one assume that if you run the FIFO RCLK off of an enabled clock then all of the logic downstream also runs on that clock?

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
11,439 Views
Registered: ‎10-11-2007

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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Turning the clocks for FIFOs off is generally not a good idea for most applications because you turn off the synchronizers in the FIFO as well as the WR/RD pointers (counters) which would result in unpredictable flag behaviour. So it's best to have some logic running synchronously on the read and write clock which control the WREN/RDEN

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Voyager
Voyager
11,428 Views
Registered: ‎02-10-2012

Re: Using Clock Signals to Drive CE Pins of FF's and Enable lines of FIFO'S

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bassman59 wrote:


arvindnr wrote:

Thanks for your reply Ralfk,

 

I am redesigning modules to use the Clock from BUFGCE and I control the CE pin of that BUFG from my divider logic.

 

I just had one lingering question which I realized yesterday : I have to drive my FIFO's implemenetd in Block RAM with my dynamically divided Clk . I can do this in 2 ways :

 

1) Drive the Clk signal of the FIFO's using my continous fast clock and drive the WR and RD enable lines of FIFO's using my BUFGCE output. That way I can control the read and write at a frequency I want by turning on and off the BUFGCE.

 

2) Second way is to directly drive the FIFO Clock input using my BUFGCE output and keep the WR and RD enables lines turned on all the time.


I'm not sure I understand why you're trying to do this. Is it a matter of not meeting timing?

 

Why not just control the RD and WR signals as necessary, running them off the RCLK and the WCLK respectively? 

 

It is not a problem with timing. I have to Write Data to the FIFO at different divided frequencies compared to my main system 100 Mhz clock. So if I have to write data at say 20 Mhz then I can either drive the WR enable of the FIFO every 5th 100 Mhz clock cycle or I can directly connect my divided 20 Mhz clock to the FIFO clock input and keep the Enables high. This process is not continous and hence the clock is not constant. Also the divided clock is dynamically changed based on inputs. So thats another factor. 


If I remember correclty I had read that the FIFO designs usually prefer continous clock and one must control the enable lines in order to read and write data at a reduced frequency from the Clock.


The FIFO clocks need not be continuous, but it helps. It makes timing analysis simpler and since the flags are dependent on the clock then if the clock stops you might not see a flag change. Tying RD true and manipulating the read clock frequency sounds a lot more difficult than asserting the RD flag when a read is necessary.

 

Can one assume that if you run the FIFO RCLK off of an enabled clock then all of the logic downstream also runs on that clock?

 

I use a common clock domain fifo design so the read and write process is synchronized to the main system clock. The downstream logic runs on the main system clock . I latch the data out from the FIFO and use it later. 

 

Any ways I decided to go with what you and ralfk suggested. Turned out manuplating the Enable lines is more easier and better compared to manuplating the clock's itself. 

 

Thanks for taking out the time to reply.

Cheers

Arvind

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