Using the USER pushbuttons as a resest?

[ftamulonis]

Hello everyone. I am currently working on a Ethernet code using the SP605 development board with the Spartan-6 XC6SLX45T. To test to make sure the reset is working I have made a process ,or its equal in verilog, that blinks an LED  on and off  ,if it dectetcs the reset is on, and turn the LED off if it is working. I am having problems with the reset : it is stuck in reset.  If it matters the clock I am using is 20Mhz dvidied down from the onboard 200Mhz .Here is the test part of the code. 

//////////////////////////////////////////////////////////////////////////////////////////

reg LED_TEST_2;

always @(posedge clkOut or posedge rst)
begin
if(rst==1'b1)
begin
LED_TEST_2=1'b1;  ///turn the Led on
#5000                          /// wait
LED_TEST_2=1'b0; ///turn the led off
#5000                         /// wait
LED_TEST_2=1'b1; /// turn the led on
end
else
begin
LED_TEST_2=1'b0; ///turn the led off
end
end

/////////////////////////////////////////////////////////

the reset is run by , or I would like it to be run by, GPIO_BUTTON_0 whose pin is F3. 

here is the UCF file. 

//////////////////////////////////////////////

# On board 200MHz clock
NET "clkIn" Loc = "K22";/// 200 Mhz Ocillator: SYSCLK_N
#Divider Clk
NET "clkOut" Loc = "P20"; /// USER_SMA_CLOCK_N
#reset momentary switch
NET "rst" LOC = "F3";
NET "Invrst" LOC = "G6";

//TEST LED TO MAKE SURE THAT INVERSE RESET and reset WORKS 
Net "LED_TEST" LOC = "D21"; ///3rd LED
NET "LED_TEST_2" LOC = "D17"; ///1st LED

//////////////////////////////////////////////

I am getting an error that the clocking place ment is wrong : 

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <rst> is placed at site <F3>. The corresponding BUFG component
<rst_IBUF_BUFG> is placed at site <BUFGMUX_X2Y2>. There is only a select set
of IOBs that can use the fast path to the Clocker buffer, and they are not
being used. You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

//////////////////////////////////////////

Right now I just want to get reset working. one that happens everything else should fall into palce.

Thank you any suggestions would be great. 

[rcingham]

I am not a Verilog expert, but even I know that 'posedge rst' causes the Synthesis and downstream tools to consider 'rst' to be a clock.

I suggest that you use it as a synchronous reset instead. You can worry about debouncing it later, if needed.

[ftamulonis]

Ok so I made this difference:

reg LED_TEST_2;
wire rst;
always @(posedge clkOut or posedge rst)
begin
LED_TEST_2 =1'b1;
end

now I am getting an error that says assignment under multiple single edges  is not supported for synthesis. 

[avrumw]

This is not synthesizable verilog. The #5000 is completely meaningless to synthesis.

Synthesis is a process in which the synthesis tool tries to replicate the functionality of your design using real hardware resources. There is no hardware resources that is a 5000 unit delay element - it doesn't exist.

Your

always @(posedge clkOut or posedge rst)

is the correct way to infer an active high asynchronous reset, but lets look at what your code does, knowing that the #5000 are completely ignored. You have multiple blocking assignments to LED_TEST_2 in the same branch of the if (rst==1) block. Since the #5000 are ignored, the last ones will override the first ones, so you end up with

always @(posedge clkOut or posedge rst)
begin
  if(rst==1'b1)
  begin
    LED_TEST_2=1'b1; 

  end

  else

  begin

    LED_TEST_2=1'b0; ///turn the led off

  end

end

Thus, on the clock after you push the rst (assuming the rst button is actually active high), the LED will come on and stay on as long as you hold the rst button. Once you release it, it will go off on the first clock where the button is seen as being released.

Avrum

[mcgett]

> now I am getting an error that says assignment under multiple single edges  is not supported for synthesis.

Likely because you have not shown the entire code and in another process you have another assignment to LED_TEST_2.

Going back to your original code it should have been this.

//////////////////////////////////////////////////////////////////////////////////////////

reg LED_TEST_2;

always @(posedge clkIn)
begin
  if(rst==1'b1)
     LED_TEST_2=1'b1;  ///turn the Led on 
  else
     LED_TEST_2=1'b0; ///turn the led off
end

/////////////////////////////////////////////////////////

 This code uses the input clock net (ClkIn), changes reset to the preferred synchronous style and removes the unsynthesizable wait statements.

[ftamulonis]

Thank you for the information. I checked the rest of the code and do not have another assignment to LED_TEST_2 other then its declaration. I also tried your code (see below ) and got my original error : 

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <rst> is placed at site <F3>. The corresponding BUFG component
<rst_IBUF_BUFG> is placed at site <BUFGMUX_X2Y4>. There is only a select set
of IOBs that can use the fast path to the Clocker buffer, and they are not
being used. You may want to analyze why this problem exists and correct it.
If this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

/////////////////// this is the modifed code

reg LED_TEST_2;

always @(posedge clkIn)
begin
if(rst ==1'b1)
LED_TEST_2 =1'b1;
else
LED_TEST_2 =1'b0;

end

//////////////////////////

if you would like to see the whole code I will attach it below. I think that it is too long for the fourms. 

[avrumw]

It is clear from this message  that the tool is seeing your rst pin as a clock pin. I don't think it is coming from this block, which looks OK (at least from the syntax point of view).

Somewhere else in your code (and I haven't opened your .xise project), you either have something like always @(posedge rst), or some kind of a latch

always @(*)

begin

  if (rst)

  begin

    some_assignment

  end

end

I also want to point out that your current code is just a single FF. Basically the code you wrote reduces to

always @(posedge clkIn)

   LED_TEST_2 = rst;

Avrum

[mcgett]

> I also tried your code (see below ) and got my original error :

Then somewhere in rest of your code that you say is too big to post is using the rst input incorrectly and it is identified as a clock.

[ftamulonis]

Going back to your orinal statment with the synchronous reset. I Tried that and there were no errors. However, when I push the GPIO_BUTTON_0 the light will not switch. In case I pushed the wrong button I tried all 3 other buttons: same story. I thinking that now it is an issue with the button.

In any case, at the end I would like it so that when I hit GPIO_BUTTON_0 the led turns on and when I release the LED should turn off. 

Thank you for you input. 

[muzaffer]

Just to make sure your code is not to blame; connect the reset signal directly to the led. ie assign led = reset;
This should enable you to do what you want mechanically. If this works, we can work on the code later.

[ftamulonis]

Thank you muzaffer. When I connect the led to the reset directly it works. 

assign LED_TEST_2 = rst. 

So does that mean there is somthing wrong with the clock or somthing else. 

[ftamulonis]

Ok so I think it is time for everyone to see the code. Just so you know it is quite big. The part that I am testing is at the bottom and is commented out right now . 

Just a note: i believe once we figure out what is wrong with the clocks/reset, everything should work.

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:40:42 07/31/2013
// Design Name:
// Module Name: packet_sender
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module packet_sender(clkIn, Ethernet_TDp, Ethernet_TDm,rst,LED_TDp,LED_TDm,clkOut,Invrst,LED_TEST_2);

// a 20MHz clock (this code won't work with a different frequency)
input clkIn; ///input is higher than 20Mhz clock divder brings it down to 20Mhz
input rst;

// the two differential 10BASE-T outputs
output Ethernet_TDp, Ethernet_TDm,LED_TDm,LED_TDp;
output Invrst;
output reg clkOut;

output LED_TEST_2;

// Source (FPGA) IP Address
parameter IPsource_1 = 169;
parameter IPsource_2 = 254;
parameter IPsource_3 = 95;
parameter IPsource_4 = 93;

// PC IP Address
parameter IPdestination_1 = 169;
parameter IPdestination_2 = 254;
parameter IPdestination_3 = 95;
parameter IPdestination_4 = 95;

// PC MAC Address
parameter PhysicalAddress_1 = 8'h3C;
parameter PhysicalAddress_2 = 8'h97;
parameter PhysicalAddress_3 = 8'h0E;
parameter PhysicalAddress_4 = 8'h5F;
parameter PhysicalAddress_5 = 8'hE4;
parameter PhysicalAddress_6 = 8'h06;

////Clock Divider (not needed with constrained clock in UCF)
assign Invrst = ~rst;

reg [3:0] count;

always @ (posedge clkIn or negedge Invrst)
begin
if (!Invrst)
begin
count<=4'd0;
clkOut <= 1'b0;
end
else
begin
if(count==4'd4)
begin
count<=4'd0;
clkOut <= ~clkOut;
end
else
begin
count<=count+1;
end

end
end

//always @(negedge clkOut or posedge rst)
//begin
//if (!rst)
//begin
//New_clk <= clkOut;
//end
//end

//////////////////////////////////////////////////////////////////////
// sends a packet roughly every second

//counter process

reg [23:0] counter;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
counter<=00000000000000000000;
end
else
begin
counter<=counter+1;
end
end
////////////////// end counter process
///// Start StartSending Process

reg StartSending;

always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
StartSending<=0;
end
else
begin
StartSending<=1;
end
end

//&counter

//////////////////////////////////////////////////////////////////////
// we send a UDP packet, 18 bytes payload

// calculate the IP checksum, big-endian style
parameter IPchecksum1 = 32'h0000C53F + (IPsource_1<<8)+IPsource_2+(IPsource_3<<8)+IPsource_4+
(IPdestination_1<<8)+IPdestination_2+(IPdestination_3<<8)+(IPdestination_4);
parameter IPchecksum2 = ((IPchecksum1&32'h0000FFFF)+(IPchecksum1>>16));
parameter IPchecksum3 = ~((IPchecksum2&32'h0000FFFF)+(IPchecksum2>>16));

reg [6:0] rdaddress;
reg [7:0] pkt_data;

always @(posedge clkOut or negedge Invrst)
case(rdaddress)
// Ethernet preamble
7'h00: pkt_data <= 8'h55;
7'h01: pkt_data <= 8'h55;
7'h02: pkt_data <= 8'h55;
7'h03: pkt_data <= 8'h55;
7'h04: pkt_data <= 8'h55;
7'h05: pkt_data <= 8'h55;
7'h06: pkt_data <= 8'h55;
7'h07: pkt_data <= 8'hD5;
// Ethernet header
7'h08: pkt_data <= PhysicalAddress_1;
7'h09: pkt_data <= PhysicalAddress_2;
7'h0A: pkt_data <= PhysicalAddress_3;
7'h0B: pkt_data <= PhysicalAddress_4;
7'h0C: pkt_data <= PhysicalAddress_5;
7'h0D: pkt_data <= PhysicalAddress_6;
7'h0E: pkt_data <= 8'h00;
7'h0F: pkt_data <= 8'h12;
7'h10: pkt_data <= 8'h34;
7'h11: pkt_data <= 8'h56;
7'h12: pkt_data <= 8'h78;
7'h13: pkt_data <= 8'h90;
// IP header
7'h14: pkt_data <= 8'h08;
7'h15: pkt_data <= 8'h00;
7'h16: pkt_data <= 8'h45;
7'h17: pkt_data <= 8'h00;
7'h18: pkt_data <= 8'h00;
7'h19: pkt_data <= 8'h2E;
7'h1A: pkt_data <= 8'h00;
7'h1B: pkt_data <= 8'h00;
7'h1C: pkt_data <= 8'h00;
7'h1D: pkt_data <= 8'h00;
7'h1E: pkt_data <= 8'h80;
7'h1F: pkt_data <= 8'h11;
7'h20: pkt_data <= IPchecksum3[15:8];
7'h21: pkt_data <= IPchecksum3[ 7:0];
7'h22: pkt_data <= IPsource_1;
7'h23: pkt_data <= IPsource_2;
7'h24: pkt_data <= IPsource_3;
7'h25: pkt_data <= IPsource_4;
7'h26: pkt_data <= IPdestination_1;
7'h27: pkt_data <= IPdestination_2;
7'h28: pkt_data <= IPdestination_3;
7'h29: pkt_data <= IPdestination_4;
// UDP header
7'h2A: pkt_data <= 8'h04;
7'h2B: pkt_data <= 8'h00;
7'h2C: pkt_data <= 8'h04;
7'h2D: pkt_data <= 8'h00;
7'h2E: pkt_data <= 8'h00;
7'h2F: pkt_data <= 8'h1A;
7'h30: pkt_data <= 8'h00;
7'h31: pkt_data <= 8'h00;
// payload
7'h32: pkt_data <= 8'h00; // put here the data that you want to send
7'h33: pkt_data <= 8'h01; // put here the data that you want to send
7'h34: pkt_data <= 8'h02; // put here the data that you want to send
7'h35: pkt_data <= 8'h03; // put here the data that you want to send
7'h36: pkt_data <= 8'h04; // put here the data that you want to send
7'h37: pkt_data <= 8'h05; // put here the data that you want to send
7'h38: pkt_data <= 8'h06; // put here the data that you want to send
7'h39: pkt_data <= 8'h07; // put here the data that you want to send
7'h3A: pkt_data <= 8'h08; // put here the data that you want to send
7'h3B: pkt_data <= 8'h09; // put here the data that you want to send
7'h3C: pkt_data <= 8'h0A; // put here the data that you want to send
7'h3D: pkt_data <= 8'h0B; // put here the data that you want to send
7'h3E: pkt_data <= 8'h0C; // put here the data that you want to send
7'h3F: pkt_data <= 8'h0D; // put here the data that you want to send
7'h40: pkt_data <= 8'h0E; // put here the data that you want to send
7'h41: pkt_data <= 8'h0F; // put here the data that you want to send
7'h42: pkt_data <= 8'h10; // put here the data that you want to send
7'h43: pkt_data <= 8'h11; // put here the data that you want to send
default: pkt_data <= 8'h00;
endcase

//////////////////////////////////////////////////////////////////////
// and finally the 10BASE-T's magic

reg SendingPacket;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
SendingPacket<=1'b0;
end
else if(StartSending)
begin
SendingPacket<=1'b1;
end
else if(ShiftCount==14 && rdaddress==7'h48)
begin
SendingPacket<=1'b0;
end
end
/////
reg [3:0] ShiftCount;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
ShiftCount<=0000;
end
else
ShiftCount <= SendingPacket ? ShiftCount+1 : 15;
end
/////

/////////////end SendingPacket Process
// Start readram process
wire readram =(ShiftCount==15);
reg [7:0] ShiftData;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
ShiftData<=00000000;
rdaddress<=0000000;
end
else if(ShiftCount==15)
begin
rdaddress <= SendingPacket ? rdaddress+1 : 0;
end
else if(ShiftCount[0])
begin
ShiftData <= readram ? pkt_data &colon; {1'b0, ShiftData[7:1]};
end
end
////end readram process

// generate the CRC32
reg [31:0] CRC;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
CRC<=00000000000000000000000000000000;
end
else if(ShiftCount[0])
begin
CRC <= CRCinit;
end
else
begin
CRC<=({CRC[30:0],1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7));
end
end

/////////
reg CRCflush;
always @(posedge clkOut or negedge Invrst)
begin
if(!Invrst)
begin
CRCflush<=0;
end
else if(CRCflush)
CRCflush <= SendingPacket;
else if(readram)
begin
CRCflush <= (rdaddress==7'h44);
end
end
//////
reg CRCinit;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
CRCinit<=0;
end
else if(readram)
begin
CRCinit <= (rdaddress==7);
end
end
wire CRCinput = CRCflush ? 0 : (ShiftData[0] ^ CRC[31]);
///End the CRC32 Process
//reg [31:0] CRC;
///reg CRCflush; always @(posedge clkOut or negedge rst) if(CRCflush) CRCflush <= SendingPacket; else if(readram) CRCflush <= (rdaddress==7'h44);
//reg CRCinit; always @(posedge clkOut or negedge rst) if(readram) CRCinit <= (rdaddress==7);
//wire CRCinput = CRCflush ? 0 : (ShiftData[0] ^ CRC[31]);
//always @(posedge clkOut or negedge rst) if(ShiftCount[0]) CRC <= CRCinit ? ~0 : ({CRC[30:0],1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7));

// generate the NLP
reg [17:0] LinkPulseCount;
reg LinkPulse;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
LinkPulseCount<=000000000000000000;
LinkPulse<=0;
end
else
begin
LinkPulseCount <= SendingPacket ? 0 : LinkPulseCount+1;
LinkPulse <= &LinkPulseCount[17:1];
end
end

// TP_IDL, shift-register and manchester encoder
reg SendingPacketData;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
SendingPacketData <= 1'b0;
end
else
SendingPacketData <= SendingPacket;
end

/////
reg [2:0] idlecount;
always @(posedge clkOut or negedge Invrst)
begin
if(!Invrst)
begin
idlecount<=00;
end
else if(SendingPacketData)
idlecount<=0;
else if(~&idlecount)
begin
idlecount<=idlecount+1;
end
end
////
wire dataout = CRCflush ? ~CRC[31] : ShiftData[0];
////
////
reg qo;
always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
begin
qo<=0;
end
else
qo <= SendingPacketData ? ~dataout^ShiftCount[0] : 1;
end
////
reg qoe;
always @(posedge clkOut or negedge Invrst )
begin
if (!Invrst)
begin
qoe<=0;
end
else
qoe <= SendingPacketData | LinkPulse | (idlecount<6);
end
//////
reg Ethernet_TDp;

always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)
Ethernet_TDp<= 1'b0;
else
begin
Ethernet_TDp <= (qoe ? qo : 1'b0);
end
end

assign LED_TDp = Ethernet_TDp; //Ethernet_TDp;

reg Ethernet_TDm;

always @(posedge clkOut or negedge Invrst)
begin
if (!Invrst)

Ethernet_TDm <= 1'b0;

else
begin
Ethernet_TDm <= (qoe ? ~qo : 1'b0);

end
end
assign LED_TDm = Ethernet_TDm;

//// Test INVERSE RST (OUTPUTS TO 3rd LED from the LEFT):::::::::::::: NOT WORKING STUCK IN INVRST

//always @( negedge Invrst)
//begin
//if (Invrst==1'b1)
//begin
//LED_TEST= 1'b1;
//#5000
//LED_TEST = 1'b0;
//#5000
//LED_TEST = 1'b1;
//end
//else
//begin
//LED_TEST = 1'b0;
//end
//end
////////////////

//// TEST RESET (OUTPUTS TO 1st LED from the LEFT)

//reg LED_TEST_2;

//always @(posedge clkIn)
//begin
//if(rst ==1'b0)
//LED_TEST_2 =1'b1;
//else
//LED_TEST_2 =1'b0;

//end
assign LED_TEST_2 = rst;  /////This works: when I press the reset button the led turns on and when I realese the button it turns off. 

endmodule

///////////////////

HERE IS THE UCF file

/////////////////////////////////////////

# PHY transmit pin 3
NET "Ethernet_TDp" Loc = "G7"; /// This pin is the PHY_TXD5 : not anymore: Y21 //
# PHY transmit pin 6
NET "Ethernet_TDm" Loc = "H6";/// This pin is the PHY_TXD2 : not anymore: AB8 //
# On board 200MHz clock
NET "clkIn" Loc = "K22";/// 200 Mhz Ocillator: SYSCLK_N
#Divider Clk
NET "clkOut" Loc = "P20"; /// USER_SMA_CLOCK_N
#reset momentary switch
NET "rst" LOC = "F3";
NET "Invrst" LOC = "G6";
# LED OUTPUTS
Net "LED_TDp" LOC = "AB4"; //// Outputs the data from Ethernet_TDp
Net "LED_TDm" LOC = "W15"; //// Outputs the data from Ethernet_TDm
//TEST LED TO MAKE SURE THAT INVERSE RESET WORKS
//Net "LED_TEST" LOC = "D21"; ///3rd LED
NET "LED_TEST_2" LOC = "D17"; ///1st LED

/////// I AM NOT USING THE BELOW CONSTRAINT///////////////////////////////////////////

#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2013/08/01
#Constrain 200MHz clock to 20MHz w/ 50% duty cycle
#NET "clkIn" TNM_NET = clkIn;
#TIMESPEC TS_clkIn = PERIOD "clkIn" 20 MHz HIGH 50%;

////////////////////////////////////

Thank you to everyone helping me solve this problem.  I hope we can get it fixed. 

[muzaffer]

>> NET "clkIn" Loc = "K22";/// 200 Mhz Ocillator: SYSCLK_N

Is this line in the UCF really accurate? You are using the negative side of a differential clock signal as your clock input? If so, obviously that is not going to work. You need a differential receiver in the fpga connected to both sides of the clock. Use an IBUFDS and a BUFG after that.

[eteam00]

Around line 122 of your code snippet, you have:

always @(posedge clkOut or negedge Invrst)
case(rdaddress)

There is no async reset statement in this process, so the synthesiser is left to infer that Invrst (or ~rst) is intended to be a clock.

-- Bob Elkind

[ftamulonis]

Hi muzaffer,

This makes sense in theory and I totally agree with you. I am a little new to verilog. How could I get two inputs (SMA_CLK_N and SMA_CLK_P) to one clkIn. 

I am probably missing somthing small but I cant see a way to do it. 

Original Post: 

>> NET "clkIn" Loc = "K22";/// 200 Mhz Ocillator: SYSCLK_N

Is this line in the UCF really accurate?

You are using the negative side of a differential clock signal as your clock input? If so, obviously that is not going to work. You need a differential receiver in the fpga connected to both sides of the clock. Use an IBUFDS and a BUFG after that.

Thanks

[muzaffer]

Instantiate an IBUFDS followed by a BUFG.
ibufds u(.i(sysclkp), .ib(sysclkn), .o(clkin_i);
bufg u1(.i(clkin_i), .o(clkin));

[ftamulonis]

Ok so I made an IBUFDS followed by a BUFG

IBUFDS IBUFDS_inst (
.clkIn_i(clkIn_i), // Clock buffer output
.CLKINP(CLKINP), // Diff_p clock buffer input (connect directly to
// top-level port)
.CLKINN(CLKINN) // Diff_n clock buffer input (connect directly to
// top-level port)
);
defparam IBUFDS_inst.IOSTANDARD = "LVDS_25";
// End of IBUFDS_inst instantiation

BUFG BUFG_inst(
.i(clkIn_i),
.o(clkIn));

I have some new inputs : 

//////////////////////////////////////////////////////////////////

module packet_sender(clkIn, Ethernet_TDp, Ethernet_TDm,rst,LED_TDp,LED_TDm,clkOut,Invrst,LED_TEST_2,CLKINP,CLKINN);

// a 20MHz clock (this code won't work with a different frequency)
input clkIn; ///input is higher than 20Mhz clock divder brings it down to 20Mhz
input rst;
input CLKINP;
input CLKINN;

//////////////////////////////////////////////////////

and finally the  pins:

# On board 200MHz clock
NET "CLKINN" Loc = "K22";/// 200 Mhz Ocillator: SYSCLK_N
NET "CLKINP" Loc = "K21";/// 200 MHz Ocillator: SYSCLK_N

That is all great. when I try to synthesize it I get some errors. 

Cannot find port clkIn_i on this module

Cannot find port CLKINP on this module

Cannot find port CLKINN on this module

I do not know why this is happening because I declared them in the beginning of the module

[gszakacs]

It's not your signals, but the port names of the IBUFDS that create the errors.  You need to use the correct port names which (from memory) are .I, .IB, and .O for input positive, input negative, and output respectively.

[mcgett]

> Cannot find port clkIn_i on this module

This should have been defined as a WIRE not an INPUT

> Cannot find port CLKINP on this module

> Cannot find port CLKINN on this module\

You did not include either of these in the module portdefinition.  Most designers combine the module port definition and the input/output/inout as one item to reduce the risk of errors like this:

module packet_sender(
input   CLKINP,
input   CLKINN,
input   rst,
output  LED_TEST_2,
..,
..,
..
);

[ftamulonis · Accepted solution]

Hi everyone

Thank you for troubleshooting this program with me. It means a lot. I just downloaded the program onto the board (after simulating ) 

and it worked. 

again Thank you so much!!!!!