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rob69
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Registered: ‎11-03-2015

VHDL FSM problem

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Dear forum

 

I'm implementig a FSM in VHDL...very simple..just some state with no condition.Every CLK it goes

in a new state. Symulation work and real circuit work also.

 

Now, I add a simple modify: I want transitate in a new state not after 1 CLK, but after 1000  CLK.

So, without annoing you with all the code, the VHDL code for one state (all other will have same VHDL but different name):

 

 ---------------------------------

  --Implement the FF........tipical code

------------------------------------

  process (CLK)
    begin
        if (CLK = '0' and CLK'event ) then
       
            StateNowOut <= StateNextLogicOut;
       
        end if;
    
    ---------------------
    --Next State Logic--
    ---------------------
       process (StateNowOut)
   
        --Local
        variable Counter :unsigned(9 downto 0):=0;
        
        begin
       
        case StateNowOut is
        
                
                  when STATE1 =>
                            
                       Counter:=Counteri+1;   
                                   
                        if ( Counter= to_unsigned (1000, Counter'length) ) then
                        
                          Counter:=0;


                            --Next
                           StateNextLogicOut<=STATE2;
                                                    
                        end if;
                       
                       
               
                 when STATE2 =>
                  ----

                 ----------

 

This code, simulate correct, but dont work in a real board.

Some strange is that i cant see in my FPGA implementation, any instantiation of a real counter..like if the variable Counter

is not considered.

 

Am I doing some basic error?

 

Thanks for your time 
                

 

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rob69
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10,229 Views
Registered: ‎11-03-2015

Thanks u42

 

you was very helpful and precise, and save me many time.

 

Thank again

 

Roberto

View solution in original post

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3 Replies
mcgett
Xilinx Employee
Xilinx Employee
6,031 Views
Registered: ‎01-03-2008

You are using a two-process state machine style and these are inherently buggy since one state is synchronous and the other is asynchronous.   In this case you have generated a clock-less counter.

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u4223374
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Registered: ‎04-26-2015

The problem is that you've specified that the combinational block ("Next State Logic") only updates when StateNowOut changes. This works in simulation, but isn't actually possible in the real world. In the real world, the combinational block will update whenever any of the inputs to that block change. In particular, "counter" is used as an input (so that you can add one to it). As a result, when you enter STATE1, the counter increments by one, which triggers it to run again and increment by 1 again, and so on - until it hits 1000 and changes to the next state. Because it's not a clocked process, this all happens instantly - in much less than one cycle.

 

The synthesis tool sees that this will happen, realises that there's no point actually having the counter if it's just going to count from 0 to 1000 in a single cycle, and removes it - which is why you can't find the counter.

 

You need to move the counter to a sequential block, so that it runs on the clock edge. The combinational state machine block can control reset/enable inputs to the counter, but it can't do the actual counting.

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rob69
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Registered: ‎11-03-2015

Thanks u42

 

you was very helpful and precise, and save me many time.

 

Thank again

 

Roberto

View solution in original post

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