cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
fpga_freak
Observer
Observer
4,952 Views
Registered: ‎11-01-2007

VHDL Generate loop index

Hi,

I am working on an HDL for an Xilinx FPGA design.

I came a situation where i want to increment vhdl generate loop index by 2.

An example is show below,

 

LABEL: for i in 1 to CNTR_WIDTH -1 generate

  REG1(i) <= ORG_REG(i)(1 downto 0);

  REG1(i+1) <= ORG_REG(i)(3 downto 2);

end generate;

 

I want the generate loop i variable index proceeds like 0,2,4,6 upto the defined range. Please help me how to do this in vhdl?

 

Regards,

freak

0 Kudos
1 Reply
pcurt
Explorer
Explorer
4,948 Views
Registered: ‎04-09-2008

You could loop half has many times and multiply by 2, instead.  That's how I would do it.

 

for i in 0 to MAX/2 generate

  REG1(i*2) <= even_values_signal_assignment;

  REG1(i*2+1) <= odd_values_signal_assignment;

end generate;

 

You'll need another generate statement to handle the special case where MAX is odd.

 

if MAX mod 2 > 0 generate

  REG1(MAX) <= odd_values_signal_assignment;

end generate;

 

Or, you could modify the original loop to iterate 0 to MAX/2+1 and qualify the even signal assignment with another if-generate.  That way, there would be only 1 "even" equation and one "odd" equation.  With the former approach, you risk modifying the odd case in the first loop and forgetting ot modify the special case following.

0 Kudos