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edwinwu
Observer
Observer
4,294 Views
Registered: ‎08-26-2010

VHDL Sensitivity list of process question

Hi all,

 

If I add signals that are not use in the process to the Sensitivity list, what will happen?

 

 

--Edwin

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awillen
Mentor
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Registered: ‎11-29-2007

During simulation, the process might be triggered more often than necessary. There won't be any consequences for synthesis.

 

 

Adrian



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drjohnsmith
Teacher
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Registered: ‎07-09-2009

as an aside, 

 

hopefully you will notice the warning given in the tools though, if not the design review might notice it !

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cobb
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Registered: ‎12-29-2010

Hi:

 

Most sinthethizers (Sinplify Pro, for instance) give you a warning concerning with that, but concerning with the RTL sim issue mentioned above:

 

Could this delay cause non realistic timing violation at comparison checks after post-layout simulation?I mean, What happens with the real delay of the signal after post layout simulation?

 

Cobb

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eteam00
Instructor
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Registered: ‎07-21-2009

Could this delay cause non realistic timing violation at comparison checks after post-layout simulation?I mean, What happens with the real delay of the signal after post layout simulation?

Theoretically anything is possible, but this is implausible.  Modern simulators are scheduled-event driven.  Triggering a process for an unused signal in the sensitivity list doesn't affect the output of the process, it just eats compute cycles in the sim engine.

 

- Bob Elkind

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