VHDL Sensitivity list of process question

edwinwu · ‎12-25-2010

Hi all,

If I add signals that are not use in the process to the Sensitivity list, what will happen?

--Edwin

awillen · ‎12-25-2010

During simulation, the process might be triggered more often than necessary. There won't be any consequences for synthesis.

Adrian

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drjohnsmith · ‎12-30-2010

as an aside,

hopefully you will notice the warning given in the tools though, if not the design review might notice it !

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cobb · ‎12-30-2010

Hi:

Most sinthethizers (Sinplify Pro, for instance) give you a warning concerning with that, but concerning with the RTL sim issue mentioned above:

Could this delay cause non realistic timing violation at comparison checks after post-layout simulation?I mean, What happens with the real delay of the signal after post layout simulation?

Cobb

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eteam00 · ‎12-30-2010

Could this delay cause non realistic timing violation at comparison checks after post-layout simulation?I mean, What happens with the real delay of the signal after post layout simulation?

Theoretically anything is possible, but this is implausible. Modern simulators are scheduled-event driven. Triggering a process for an unused signal in the sensitivity list doesn't affect the output of the process, it just eats compute cycles in the sim engine.

- Bob Elkind

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