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Visitor jan.acosta
Visitor
9,953 Views
Registered: ‎12-03-2010

VHDL help

Hello,

 

I am currently having trouble trying to implement a calculator that multiplies two 4-bit values.

 

The calculation is easy, but what I need to do is output the answer to 4 seven segment displays.

 

SInce there are about 255 possible answers when multiplying two 4-bit values, how do I write VHDL code without having to write each possble answer and assign a number to each of the seven segment displays?

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9 Replies
Scholar joelby
Scholar
9,948 Views
Registered: ‎10-05-2010

Re: VHDL help

Do you want to display the result in base 10? You should only need three displays.

 

You'll want to convert the number to BCD, which means that your three digit number is stored in three four-bit registers, representing 100s, 10s, and 1s.

 

Divide n by 100, put the modulo in the first register. Divide the remainder by 10, put the modulo in the second and the remainder in the third. Then you'll only need to define ten 7-segment outputs.

 

Figuring out how to do this will be a fun VHDL exercise! Alternatively, you could cheat and Google it.

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Instructor
Instructor
9,944 Views
Registered: ‎08-14-2007

Re: VHDL help

Another method may be to convert the 4-bit inputs to decimal and then implement a

decimal multiplier...

-- Gabor
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Teacher rcingham
Teacher
9,939 Views
Registered: ‎09-09-2010

Re: VHDL help

I cheated and Googled for a synthesizeable binary-to-BCD converter and am very happy with it...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Teacher eteam00
Teacher
9,935 Views
Registered: ‎07-21-2009

Re: VHDL help

joelby,

 

I think it is despicable that Gabor and rcingham are doing this fellow's homework assignment.  I am shocked... SHOCKED!

 

Otherwise I would have suggested using a 256x12 Block RAM for the multiply and BCD conversion.  But I won't, because I am above that sort of thing.

 

-- Bob Elkind

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Visitor jan.acosta
Visitor
9,924 Views
Registered: ‎12-03-2010

Re: VHDL help

Haha, I misread my homework assignment's requirements.  

 

I am supposed to show the Hex value not the decimal value. 

 

I figured that out already.  I have other problems now which I can't seem to figure out a way to trouble shoot.  

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9,615 Views
Registered: ‎01-21-2013

Re: VHDL help

I need help for developing VHDL code for the solution of 3D Helmholtz wave equation using Green's function.I'm attatching the doc .

Tags (2)
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Highlighted
Newbie zgd2449
Newbie
9,511 Views
Registered: ‎04-04-2013

Re: VHDL help

If any one can help me to solve this problem please 

Develop a behavioral VHDL model of a synchronous (clocked) 2-digit, modulo-16 binary-coded-decimal (BCD) up counter. The counter should count from 0 up to 15 and then continue from 0 again. The counter should have an active high CLR signal to reset its contents to 0 at any time. The counter's state should be displayed on the 7-segment display module of the Nexys 2 Board. Both the CLK and the CLR signals should be mapped to pushbuttons, respectively. Note: when using signal CLOCK from a bush button for clocking your circuit you must add the statement NET "CLOCK" CLOCK_DEDICATED_ROUTE = FALSE; to your .ucf file. You should implement this counter using the FPGA, the 7-segment display and push-buttons on your Nexys 2 Board.
a) Turn in a hard copy of the .vhd and .ucf files for your design, respectively. 
b) Map your circuit to the Xilinx FPGA chip that is located on your FPGA
Development Board by running the Implement step. Before doing so, add a User
Constraints (.ucf) file to your project to make proper pin assignments for your
designs. The Master .ucf file for the Nexys 2 Board is available through the Class
Web Page. However, you need to edit it to keep only those signals that are defined in
your .vhd file. Turn in only the device utilization and used pin assignments
sections, respectively, of the Pad Report. 
Email : mass1311@yahoo.com

Tags (1)
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Historian
Historian
9,506 Views
Registered: ‎02-25-2008

Re: VHDL help


@zgd2449 wrote:

If any one can help me to solve this problem please 

Develop a behavioral VHDL model of a synchronous (clocked) 2-digit, modulo-16 binary-coded-decimal (BCD) up counter. The counter should count from 0 up to 15 and then continue from 0 again. The counter should have an active high CLR signal to reset its contents to 0 at any time. The counter's state should be displayed on the 7-segment display module of the Nexys 2 Board. Both the CLK and the CLR signals should be mapped to pushbuttons, respectively. Note: when using signal CLOCK from a bush button for clocking your circuit you must add the statement NET "CLOCK" CLOCK_DEDICATED_ROUTE = FALSE; to your .ucf file. You should implement this counter using the FPGA, the 7-segment display and push-buttons on your Nexys 2 Board.
a) Turn in a hard copy of the .vhd and .ucf files for your design, respectively. 
b) Map your circuit to the Xilinx FPGA chip that is located on your FPGA
Development Board by running the Implement step. Before doing so, add a User
Constraints (.ucf) file to your project to make proper pin assignments for your
designs. The Master .ucf file for the Nexys 2 Board is available through the Class
Web Page. However, you need to edit it to keep only those signals that are defined in
your .vhd file. Turn in only the device utilization and used pin assignments
sections, respectively, of the Pad Report. 
Email : mass1311@yahoo.com


Your professor has been notified of your attempt to cheat. 

Expect a failing grade for this semester.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
9,497 Views
Registered: ‎12-31-2012

Re: VHDL help

Hmmm... For fun I did your assignment in about 1hr. Maybe you should drop the class, it's only going to get harder from here. 

---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
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