VHDL srl error

[nju044]

Hello, everyone:

I came across an error when  running XST synthesis. It said "srl can not have such operands in this context."

I refered to VHDL reference book but it didn't help, so I try to turn to you.

The line having the error is as follows:

slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7) srl 1;

Thanks in advance!

[eilert · Accepted solution]

Hi,

SRL & Co. are neither supported by the std_logic packages nor by numeric_std packages. They only work on boolean and bit types. 

instead use this:

 slv_reg0(byte_index*8 to byte_index*8+7) <= '0' & Bus2IP_Data(byte_index*8  to byte_index*8+7-1); -- rightmost value is lost, leftmost value replaced by '0', all others shifted to the right.

Have a nice synthesis

  Eilert

[nju044]

Hi, eilert:

Thanks for your help. Problem solved.