Overall the schematic looks good but that's still only a small part of the design.
I would also run the proposed DDR4 interface pinouts through the tools with an example design to see if they are following all the Pin and Bank rules called out in PG150 (link is in my signature).
Next I would make sure the PCBA layout is following the DDR4 layout guidelines called out in Chapter 2 of UG583 and to double check the power design of the board to make sure it has the minimum amount of decoupling capacitors for the FPGA power rails as described in Chapter 1. There's a link to UG583 in my signature.
Overall the schematic looks good but that's still only a small part of the design.
I would also run the proposed DDR4 interface pinouts through the tools with an example design to see if they are following all the Pin and Bank rules called out in PG150 (link is in my signature).
Next I would make sure the PCBA layout is following the DDR4 layout guidelines called out in Chapter 2 of UG583 and to double check the power design of the board to make sure it has the minimum amount of decoupling capacitors for the FPGA power rails as described in Chapter 1. There's a link to UG583 in my signature.
