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Visitor
Visitor
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Registered: ‎10-03-2018

VU7P Schematic Review-Memory portion

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Hi,

Can you help me to review the schematics of VU7P FPGA interface to DDR4 & NOR flash from Micron.

Schematics attached for reference.

 

regards

Aji

 

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Moderator
Moderator
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Registered: ‎11-28-2016

Hello @ajivs,

 

Overall the schematic looks good but that's still only a small part of the design.

I would also run the proposed DDR4 interface pinouts through the tools with an example design to see if they are following all the Pin and Bank rules called out in PG150 (link is in my signature). 

 

Next I would make sure the PCBA layout is following the DDR4 layout guidelines called out in Chapter 2 of UG583 and to double check the power design of the board to make sure it has the minimum amount of decoupling capacitors for the FPGA power rails as described in Chapter 1.  There's a link to UG583 in my signature.

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Moderator
Moderator
764 Views
Registered: ‎11-28-2016

Hello @ajivs,

 

Overall the schematic looks good but that's still only a small part of the design.

I would also run the proposed DDR4 interface pinouts through the tools with an example design to see if they are following all the Pin and Bank rules called out in PG150 (link is in my signature). 

 

Next I would make sure the PCBA layout is following the DDR4 layout guidelines called out in Chapter 2 of UG583 and to double check the power design of the board to make sure it has the minimum amount of decoupling capacitors for the FPGA power rails as described in Chapter 1.  There's a link to UG583 in my signature.

View solution in original post

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