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vsau
Visitor
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Registered: ‎05-26-2011

Vector array use in a buffer (as opposed to two dimensional array)?

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I am curious on proper syntax for vector arrays?

 

I am trying to add a small memory buffer (stereo 16 samples 24bits per channel). On clk samples would go in and shift right in the buffer.

 

Suggestion on this thread: http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368 said not to use two dimensional arrays but use a one dimensional array of appropriate depth(24 in my case).

 

Unfortunately, I get the following error when attempting to compile:

ERROR:HDLCompilers:26 - "mem_buf.v" line 26 expecting ')', found '['

 

How do I correctly make the output buffer?

PS. I assume, shifting is also not correct

PSS this is on ISE Webpack 12.4

 

module mem_buf(
    input clk,
input reset, input [23:0] l_data, input [23:0] r_data,
Line 26 ---- output [15:0] r_buf[23:0],
output [15:0] l_buf[23:0] ); reg [15:0] r_bufreg[23:0]; reg [15:0] l_bufreg[23:0]; always @(posedge clk) if (reset) begin r_bufreg <=0; //FIXME need 16x24 bit zero ? l_bufreg <=0; end else begin r_bufreg <= {r_data, r_bufreg[15:1]}; //TODO is this correct? l_bufreg <= {l_data, l_bufreg[15:1]}; end assign r_buf = r_bufreg; assign l_buf = l_bufreg; endmodule

 

 

 

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gszakacs
Professor
Professor
3,618 Views
Registered: ‎08-14-2007

Verilog ports can be vectors, but not arrays.  So any range (and there can only be one range)

must come before the port name like:

 

  output reg [WIDTH-1:0] foobar,

 

You have a line:

 

output [15:0] l_buf[23:0]

 

which defines an array of vectors.  If you really need the port to transmit all

16 x 24 bits, then you need to write something like:

 

output reg [(16 * 24 - 1):0] l_buf

 

if internally you have an array, say l_buf_i, defined as:

 

reg [15:0] l_buf_i [23:0];

 

then you can use a loop like:

 

always @*

begin: named_process

  integer i;

  for (i = 0;i < 24;i = i + 1) l_buf[i*16 +: 16] = l_buf_i[i];

end

 

Note that the 16 and 24 in the above code example could be made into parameters

for a more general case.

 

HTH,

Gabor

 

output [15:0] l_buf[23:0]
-- Gabor

View solution in original post

2 Replies
gszakacs
Professor
Professor
3,619 Views
Registered: ‎08-14-2007

Verilog ports can be vectors, but not arrays.  So any range (and there can only be one range)

must come before the port name like:

 

  output reg [WIDTH-1:0] foobar,

 

You have a line:

 

output [15:0] l_buf[23:0]

 

which defines an array of vectors.  If you really need the port to transmit all

16 x 24 bits, then you need to write something like:

 

output reg [(16 * 24 - 1):0] l_buf

 

if internally you have an array, say l_buf_i, defined as:

 

reg [15:0] l_buf_i [23:0];

 

then you can use a loop like:

 

always @*

begin: named_process

  integer i;

  for (i = 0;i < 24;i = i + 1) l_buf[i*16 +: 16] = l_buf_i[i];

end

 

Note that the 16 and 24 in the above code example could be made into parameters

for a more general case.

 

HTH,

Gabor

 

output [15:0] l_buf[23:0]
-- Gabor

View solution in original post

vsau
Visitor
Visitor
2,910 Views
Registered: ‎05-26-2011

Thank you for the quick reply!

 

I made the appropriate changes to my code per your suggestions.

 

Also, I decided not to output whole port width outside the module. I can do what I need to do inside the module and just output the result which is only (24 bits wide).

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