Verilog-AMS synthesis

[mschreiber68]

Hi all!

I have been looking into Verilog-AMS recently so I can add analog behavior into my FPGA design. Are Xilinx FPGAs compatible with this? Will ISE synthesize it? Or does anyone have advice or experience using Verilog-AMS?

Thanks,

Mike

[eilert · Accepted solution]

Hi Mike,

you can't add analog behaviour to a digital device by choosing a different language.

The AMS languages are an approach to allow mixed mode simulations even on a macroscopic level.

Good old Spice has its's limitations to microelectronics and couldn't handle digital simulation well (took too much time).

Matlab & Co. are able to solve lots of differential equations, but it's a fully commercial product & language.

So, standardized laguages like VHDL and verilog came into the focus. They already could handle the digital stuff very well. 

VHDL already knew units. So it was possible (while not easy) to expand these languages and tools with analog properties.

Even if one day Field Programmable Analog Arrays mature, the synthesis support via AMS languages will only use a well defined subset.

For now you can forget synthesizing AMS languages and be glad if you have a fully working AMS-simulator.

Have a nice simulation

  Eilert