UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
1,057 Views
Registered: ‎01-13-2018

Verilog to VHDL Translator

Hello, 

Is there any way to add Verilog source code files in Vivado or in any other tool which convert the Verilog code to VHDL ? 

0 Kudos
5 Replies
Scholar dpaul24
Scholar
1,045 Views
Registered: ‎08-07-2014

Re: Verilog to VHDL Translator

@joniengr081,

Mixed language sim is supported by most simulator tools. So why is this needed?

Best way to convert is manual convert.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Voyager
Voyager
1,007 Views
Registered: ‎05-21-2015

Re: Verilog to VHDL Translator

It might be easier to convert from VHDL to Verilog.  Have you tried vhdl2vl at all?

Tags (1)
0 Kudos
Scholar drjohnsmith
Scholar
990 Views
Registered: ‎07-09-2009

Re: Verilog to VHDL Translator

Verilog is a lot more 'fluid' than VHDL , which is strongly typed .

As such, the variability in verilog make sit very hard to auto convert to VHDL, where as , as pointed out , VHDL to Verilog is possible to auto convert.
0 Kudos
Explorer
Explorer
871 Views
Registered: ‎01-13-2018

Re: Verilog to VHDL Translator

Hi again, 

Thanks for reply. Is it possible to write test bench in VHDL in Questa for a Verilog source code file ? In this way the behavior of Verilog source code will be known. 

0 Kudos
Scholar drjohnsmith
Scholar
840 Views
Registered: ‎07-09-2009

Re: Verilog to VHDL Translator

If your questa is multi language capable, then yes , that's quite normal.
0 Kudos