12-14-2018 05:20 AM
Is there any way to add Verilog source code files in Vivado or in any other tool which convert the Verilog code to VHDL ?
12-14-2018 05:55 AM - edited 12-14-2018 05:55 AM
Mixed language sim is supported by most simulator tools. So why is this needed?
Best way to convert is manual convert.
12-14-2018 10:11 AM
12-17-2018 03:32 AM
Thanks for reply. Is it possible to write test bench in VHDL in Questa for a Verilog source code file ? In this way the behavior of Verilog source code will be known.