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Observer mikezgrt
Observer
3,918 Views
Registered: ‎03-05-2014

Vivado 2013.4 ILA v3.0 implementation error- FIFO_GENERATOR_V10_0 not found

I have a raw Vivado 2013.4 installation, and as of today I see there are no service packs for it, so here is my problem.

 

I have generated an ILA (V3.0 is the only version included in my current Vivado catalog).  Instantiated the ILA.  It synthesized just fine, but during implementation I get the following errors.

 

Time (s): cpu = 00:00:00 ; elapsed = 00:00:11 . Memory (MB): peak = 1082.781 ; gain = 0.148
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 93 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design failed
Implementing debug core dbg_hub failed.
ERROR: [Chipscope 16-133] Failed to generate and synthesize debug IP "xilinx.com:ip:labtools_xsdb_master_lib:2.0".
ERROR: [IP_Flow 19-617] Could not find core reference 'xilinx.com:ip:fifo_generator:10.0', your sources may be incomplete.
ERROR: [Synth 8-439] module 'FIFO_GENERATOR_V10_0' not found [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/xsdb_wrfifo.v:288]
ERROR: [Synth 8-285] failed synthesizing module 'xsdb_wrfifo' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/xsdb_wrfifo.v:75]
ERROR: [Synth 8-285] failed synthesizing module 'icon_datawr_reg' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/icon_datawr_reg.v:78]
ERROR: [Synth 8-285] failed synthesizing module 'icon_interface' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/icon_interface.v:78]
ERROR: [Synth 8-285] failed synthesizing module 'chipscope_icon2xsdb_mstrbr' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/chipscope_icon2xsdb_mstrbr.v:78]
ERROR: [Synth 8-285] failed synthesizing module 'labtools_xsdb_master_lib' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/labtools_xsdb_master_lib_v2_0/hdl/verilog/labtools_xsdb_master_lib.v:76]
ERROR: [Synth 8-285] failed synthesizing module 'dbg_hub_CV' [e:/KC705_DevKit_V100_R3_GT_MEMC_INITIAL_NO_XCVR/KC705_a818_core.runs/impl_4/.Xil/Vivado-2684-/dbg_hub_CV_1/dbg_hub_CV.srcs/sources_1/ip/dbg_hub_CV/synth/dbg_hub_CV.v:57]
ERROR: [Common 17-39] 'source' failed due to earlier errors.
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed



    while executing
"opt_design "
INFO: [Common 17-206] Exiting Vivado at Thu Mar 27 09:42:52 2014...

 

 

The problem, is that I don't have FIFO_GENERATOR_V10_0 in my IP catalog.  The directory exists in the Xilinx Vivado DATA IP directory on my Hard Drive but is not populated.  I have V11_0, but not 10.  I have scoured the net as to how to populate the fifo generator v10 on my own, but I can't find a single thread on how to do this.  So In summary, Xilinx is providing a core that points at another core they do not provide any longer.   How so I get around this?  I must be the only one having this problem, as I can't imagine no one has posted on this - and yes I did look at lenght for this issue in forums and the ARs.

 

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3 Replies
Observer mikezgrt
Observer
3,869 Views
Registered: ‎03-05-2014

Re: Vivado 2013.4 ILA v3.0 implementation error- FIFO_GENERATOR_V10_0 not found

OK I found my issue.  For some reason, I had a corrupt installation.  My FIFO_GENERATOR_V10 folder did exist in the IP/data directory, but was not fully populated - thus the tool not finding V10 fifo.  I reinstalled Vivado (in a temp dir) to see if this was natively how it was delivered, and saw that the V10 folder was fully populated in the new install.  Copied the V10 over and hopefully no more issues. 

Newbie ihart123
Newbie
3,300 Views
Registered: ‎05-28-2014

Re: Vivado 2013.4 ILA v3.0 implementation error- FIFO_GENERATOR_V10_0 not found

I have this same problem.  I see this error message:

 

INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'srio_gen2_0'...

ERROR: [IP_Flow 19-617] Could not find core reference 'xilinx.com:ip:fifo_generator:10.0', your sources may be incomplete.

 

This error is blocking me from building the Vivado SRIO IP.

 

I DO have the:

/brewhouse/cad5/Xilinx/Vivado/2014.1.siro_fix/data/ip/xilinx/fifo_generator_v10_0 directory and it looks like all the files in it are correct.  They look the same as in the fifo_generator_v10_0 directory.

 

We tried reinstalling Vivado and it made no difference.

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Xilinx Employee
Xilinx Employee
3,286 Views
Registered: ‎08-01-2008

Re: Vivado 2013.4 ILA v3.0 implementation error- FIFO_GENERATOR_V10_0 not found

You need to make sure you have enough memory in tmp folder.

The other thing i would recommend you to use latest version of vivado.
Thanks and Regards
Balkrishan
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