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Participant
Participant
2,524 Views
Registered: ‎10-05-2014

Vivado checks pin io-standard in opt_design phase .... TOO LATE ...

It is very annoying to get an error message for a wrong IO STANDARD when the synthesis (that can be very long) has already completed. Then, if you correct the IO STANDARD, the synthesis starts again.

Is it possible that an easy thing like checking IO STANDARDS cannot be checked before even starting the synthesis?

At least put a "Validate pinout" button somewhere.

Is it so difficult ?

 

Regards,

Antonio.

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Vivado checks pin io-standard in opt_design phase .... TOO LATE ...

Hi @antonio.dibacco,

 

No, there is no pinout verification before synthesis.

 

However what you can do is disable the xdc file with your physical constraints for synthesis. This way if you change something in your constraints you don't have to re-run synthesis.

 

Just unselect used in synthesis for the file:

used_in.JPG

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant
Participant
2,499 Views
Registered: ‎10-05-2014

Re: Vivado checks pin io-standard in opt_design phase .... TOO LATE ...

That's a nice trick, thank you very much.

Anyway I would include some pinout validation tool, I mean the normal checks that vivado does while placing phase but available to be executed when the user changes something in the XDC file.

 

Regards,

Antonio.

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Moderator
Moderator
2,493 Views
Registered: ‎11-09-2015

Re: Vivado checks pin io-standard in opt_design phase .... TOO LATE ...

Hi @antonio.dibacco,

 

You can use report_drc. However I am not sure what it will report after opt_design.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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