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Visitor pfxr
Registered: ‎06-11-2014

Vivado issue repackaging IP


I'm a new to FPGA's and Vivado, and i recently bought a microzed board.
I was trying to make a connection from PS to PL and make a simple calculator to start. So I've done this:



And then I sythesized, implemented and exported bitstream to SDK. In SDK i ran the self-test of the block and it says it passed. Just like in here:


Til here everything was fine, but then i wanted to change the block code so i could implement my calculator, and here is where I'm stuck. I right click the block on Vivado and click "Edit IP in Packager", here I change the code and it doesn't matter how much I change it because the changes won't be recognized.

I mean, when I repackage it after the changes are made, I do all the steps above (Synthesis, Implementation and bitstream), but when I write the code in C on SDK the changes I've made in the code of my block aren't there, the Self-test always passes and i can't implement the calculator.
I've tryed to change all the code that was in the block so I was sure that the Self-Test was going to fail, but it doesn't fail...

Am I missing some step while repackaging the block or something?

I would really appreciate some help here.

Sorry for my bad english,

Pedro Rodrigues

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2 Replies
Registered: ‎01-16-2013

Re: Vivado issue repackaging IP


I have come across one issue in that after edit and re-package IP tool create new file sets and without removing the older one and tool uses older one for the simulation. I guess in your case same this is happening.

Workaround: Please try to edit and repackage IP by changing version number. so tool will pick bigger version (i.e. latest one)

Hope it will work.

Visitor pfxr
Registered: ‎06-11-2014

Re: Vivado issue repackaging IP

Thanks for your reply :)
Sadly, I'm still stuck with the same problem. The changes i do in the block aren't doing any efect.

P.S. I've marked this as solved but it was my mistake. Sorry

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