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vaibhav.ghavat28@gmail.com

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12-26-2014 06:21 AM

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Registered:
11-25-2013

sir

I am using IP CORE component for the implementation of 64 point FFT;

So whole structure get divided into the stage-0,stage-1,stage-2.

I have given input to the all respective stages and simulate seperately and get desired result.

BUT when i simulating top module which content all trhree stages giving such warning during simulation.

at 1120 ns(1), Instance /sfg_radix_8/level_2/ADD_1/sub_0/sub_fp/U0/FP_OP/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 1120 ns(1), Instance /sfg_radix_8/level_2/ADD_1/sub_0/sub_fp/U0/FP_OP/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

so please help me to sourt out problem.

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bassman59

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12-26-2014 08:43 AM

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Registered:
02-25-2008

@vaibhav.ghavat28@gmail.com wrote:

sir

I am using IP CORE component for the implementation of 64 point FFT;

So whole structure get divided into the stage-0,stage-1,stage-2.

I have given input to the all respective stages and simulate seperately and get desired result.

BUT when i simulating top module which content all trhree stages giving such warning during simulation.

at 1120 ns(1), Instance /sfg_radix_8/level_2/ADD_1/sub_0/sub_fp/U0/FP_OP/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

so please help me to sourt out problem.

wow, the Xilinx IP cores STILL use the deprecated std_logic_arith libraries. Xilinx, get on the stick! It's almost 2015, and that old stuff is 20 years out of date!

Anyways, to answer the question: You're trying to do math. For whatever reason, the core expects inputs which are std_logic_vector. As you should know, the std_logic types has nine possible values defined.

As you should also know, no math operators are defined for std_logic and std_logic_vector, which is why Xilinx uses the (obsolete, problematic, deprecated) std_logic_arith and std_logic_signed/unsigned libraries. Those libraries include a conversion function, CONV_INTEGER(), which does as you expect: it converts a std_logic_vector in an integer. (Quick question: is that integer signed or unsigned?)

Since 'W', 'U', 'X' and 'Z' don't map obviously to any valid logic state, CONV_INTEGER() complains, which is reasonable, because it can't come up with a good result.. But in addition to complaining, it assumes a default of '0'.

The solution to your problem is to make sure that the inputs to the function are always reasonable logic states which can work out to be '0' or '1'.

----------------------------Yes, I do this for a living.

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