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newhunt163
Observer
Observer
6,382 Views
Registered: ‎02-26-2014

Whether CE or Reset/SET?

Hello:      

          After reading <WP272--Get Smart About Reset--Think Local, Not Global>, <WP275--Get your Priorities Right – Make your Design Up to 50% Smaller>, Now I come in to a new problem,     

         This question is that I want to realize function when it is synchronous on rising clk

control-A      control--B     input    output

1                      x                   x            0

0                      0                   x            0

0                      1                   C           C     

 

     Now I have two ways to realize in VHDL. The first is as follows:

process(clk)

begin    

         if (rising clk) then         

                if (A='1')   then                 

                       output <= '0';        

                else                

                        if( B= '1') then                         

                                  output <= C;                

                        end if;        

                end if;   

         end if;

end process;  

 

          This method in ISE will lead to a FF with reset. However accodring to WP275--Get your Priorities Right – Make your Design Up to 50% Smaller>>, Reset will lead to more resource in waste.  

 

       So the second way is 

process(clk)

begin    

        if (rising clk) then         

                if (A='0' and B= '1' ) then                 

                              output <= C;        

                end if;   

        end if;

end process;   

      

       Obviously, the second way will lead to a CE contorl and CE= (not A) and B, where can't have a reset/set control.Comparing with the first method, the second one have no reset/set , but use a logic function. Of course, the logic function "and" should be completed by a LUT.     

       Now My question is I want to use smaller resource and higher speed. But the first way will use reset/set ,although no  logic delay. However the second way will use a LUT and again a logic delay.    

        So which way should be recommended?     

        Can you compare the two ways in resource utilization and in speed taking platform Virtex-6 or Spatan-6?   

 

Thankks

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6 Replies
bassman59
Historian
Historian
6,362 Views
Registered: ‎02-25-2008


@newhunt163 wrote:

Hello:      

       Obviously, the second way will lead to a CE contorl and CE= (not A) and B, where can't have a reset/set control.Comparing with the first method, the second one have no reset/set , but use a logic function. Of course, the logic function "and" should be completed by a LUT.     

       Now My question is I want to use smaller resource and higher speed. But the first way will use reset/set ,although no  logic delay. However the second way will use a LUT and again a logic delay.    

        So which way should be recommended?     

        Can you compare the two ways in resource utilization and in speed taking platform Virtex-6 or Spatan-6?   

 


You might be surprised by what the synthesizer does with any particular logic description. Remember that in front of each flop's D input is a four- or five- or six-input LUT (as well as some muxes), which can implement fairly complex logic, more than just simple AND gates. It may very well be able to work out the desired logic without using either the flop's CE or the sync set/reset inputs. Or it might split up the logic in ways you don't expect.

 

Also don't forget that the set/reset input doesn't have to come from a global-ish resource; it can come from the logic that drives it, which may very well be in the same slice.

 

What you should do is write some code, fire up XST, and see what it does.

 

And when designing, write code that the human reader can understand well, and be concerned with this sort of detailed optimization only if you fail to meet timing or you run out of resources. In the vast majority of cases, neither will be an issue.

----------------------------Yes, I do this for a living.
ddemmin
Participant
Participant
6,360 Views
Registered: ‎02-10-2009

Your two code snippets are not functionally equivalent.  The second one will only output C or keep the previous value of C.  I think you mean:

process(clk)

begin    

        if (rising clk) then         

                if (A='0' and B= '1' ) then                 

                              output <= C;

                else

                              output <= 0;

                end if;   

        end if;

end process;   

 

I am not sure how the synthesizer/mapper works with each but there is a good chance both would create the same implementation.

 

I do not think those white papers are discouraging you from using set/reset functionalily.  They are saying dont use reset/set where it is not needed, the logic will come up in a known state.

 

The first question you should ask is how much optimization do you really need.  If your design fits and meets timing then you may not want to worry about it too much.  Of course you still want to follow good design practices.

 

Next you can look at the Slice structure for the architecture you are targeting.   After map you can see how various coding styles are implemented with planahead or fpgaeditor.

 

**Update: now I see bassman's reply.  Good stuff there too.  Try it, and if you dont need to follow good general practices and dont sweat the minutia (unless you need to).

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bassman59
Historian
Historian
6,355 Views
Registered: ‎02-25-2008


@ddemmin wrote:

 

I do not think those white papers are discouraging you from using set/reset functionalily.  They are saying dont use reset/set where it is not needed, the logic will come up in a known state.


The recommendation is to not use a global reset, because the configuration does indeed ensure the logic comes up in a known state. Obviously, logic blocks may need a local reset, depending on the design requirements. 

 

I think the real advice here is: "don't overthink it!"

----------------------------Yes, I do this for a living.
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muzaffer
Teacher
Teacher
6,343 Views
Registered: ‎03-31-2012

The behavior of the two blocks is not same. In one case there is a zero assignment to output (first), in the other case output remembers its previous value (second). It's difficult to compare implementation of things which behave differently.
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newhunt163
Observer
Observer
6,324 Views
Registered: ‎02-26-2014

 First, thank you for the reply to my question.

Secondly, I am sorry for my mistake that function table is different from my VHDL code.

Thirdly, I must use a simpler example to expalin my question.

          Usually, if there is a control making "output = '0' such reset/set conrtol ,then that can be often tranformed into the logic control.Taking example:

process(clk)

begin

      if( rising_edge(clk) then

         if ( A= '1') then

            output <= '0';

         else

            output <= B;

         end if;

     end if;

end process;

 

      On the basis of my understaning to ISE synthesize,the VHDL code will be synthesized to a FF with reset and the input to the FF is B; So in this way We can realize function Only using one FF.

 

     But if we transform the reset control into the logic control , We can write it to the second way:

process(clk)

begin

      if( rising_edge(clk) then

        output <= ( A= '0') and B;

     end if;

end process;

 

     In this VHDL code, ISE will  synthesize it to : use LUT to realize the logic function (A='0') and B, after the LUT's output is the FF without reset/set. So the second way will use a  LUT and a FF.

     Comparing with the first code, the different is the first one use only one FF,but the FF has a reset/set, However, the second way is to use a LUT and a FF without reset/set.

      So my question is

1) according to the <XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices v13.1>>Page 128: Chapter 7:Flip-Flops and Registers Control Signals:,this guideline is " Whenever possible, avoid operational set/reset logic altogether.".

so which  are code styles recommended? Why?

 

2)  If We map the two code styles into the real hardware , for example Virtex-6,, according to the <ug364--Virtex-6 FPGA CLB User Guide>Page 12: Storage Elements-----The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice.

     So if a FF has been used a reset/set or CE, then for Virtex-6, the remaining seven FF in the same slice cann't be used,but the four LUT still have chance to be used , This is right in map?

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bassman59
Historian
Historian
6,319 Views
Registered: ‎02-25-2008


@newhunt163 wrote:

 

1) according to the <XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices v13.1>>Page 128: Chapter 7:Flip-Flops and Registers Control Signals:,this guideline is " Whenever possible, avoid operational set/reset logic altogether.".

so which  are code styles recommended? Why?


 

Why? I think because that the guidelines are concerned with absolute maximum possible performance, which ignores the reality that most timing constraints are not pushing the designs to the device limits.

 

Version 14.1 of this document has softened that guideline to "Avoid operational set/reset logic whenever possible."

 


2)  If We map the two code styles into the real hardware , for example Virtex-6,, according to the <ug364--Virtex-6 FPGA CLB User Guide>Page 12: Storage Elements-----The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice.

     So if a FF has been used a reset/set or CE, then for Virtex-6, the remaining seven FF in the same slice cann't be used,but the four LUT still have chance to be used , This is right in map?


I'm looking at the S6 SLICEL and SLICEM diagram, and indeed, the flops' CE and SR inputs are common. What this means is that if any flops in the slice which need to use CE and/or SR must have the same CE/SR requirements. (The clock, and the clock polarity, for all flops in the slice must be the same, too.) It is certainly possible for some of the flops in the slice to not use the CE input while others do. 

 

Also note that the CE and SR signals are inputs to the slice, which means that necessarily any logic used to derive them must come from another slice; there isn't any way to use the slice's LUTs for the CE while also using those LUTs for the D inputs to the flops.

 

So, again, I think that these level of concern about wringing the last bit of performance and resource usage out of a given device is overblown. You shouldn't get lost in the weeds of this fine-level of detail. Write your code so that it's functionally correct and easy for the human reader/maintainer to understand. The vast majority of designs don't have to run "as fast as possible," they just need to meet timing. Optimize only if you fail to close timing or if you have routing/area issues. 

----------------------------Yes, I do this for a living.
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