12-04-2013 11:53 PM
I am currently working on a custom board with multiple (9) Zynq FPGAs. Our design contains a local USB bus with FT4232 devices mastering the JTAG interfaces for 8 of the Zynq FPGAs. This USB bus is mastered by the 9th Zynq device which serves as the board manager. The 9th zynq hosts a piece of software which uses the Xilinx Virtual Cable protocol (XVC) to bridge between the ISE tools and the FT4232 USB devices. The XVC protocol is described here:
This arrangement works well and allows us to debug the Zynq devices using both chipscope and XMD while requiring only a network interface between the server running the Xilinx tools and the Zynq based design. The XVC bridge software operates the FT4232 device in "bit bang" mode which is not very efficient but gets the job done.
I have not yet been able to figure out how to make this work with the Vivado logic analyzer tools. I fear that XVC support may have been dropped in Vivado. Is there any chance this interface will be supported?
04-15-2014 07:20 PM
This seems like a very straightforward question, one which I have too. Could a Xilinx rep please reply? Is this in Vivado 2014.1?
04-22-2014 07:47 AM
Digging a little deeper (and poking around my brand-new Vivado installation), I see that Xilinx now routes all hardware interactions, including JTAG, through a server process that uses the Eclipse Foundation's "Target Communication Framework." The TCF exchanges happen over TCP/IP so there is network transparency and remote-debug capability built in from the start. Cool.
I would like to know if Xilinx plans to publish their TCF protocol extensions so that users can develop interoperable implementations of the hardware server. This would be of interest to the OP, and a lot of other folks too. Or, will the extensions be left undocumented to prevent a new rash of cheap USB platform cable clones? (although looking at ebay that battle seems lost already)
I suppose it is too much to ask for a Xilinx rep to actually monitor and reply in the forums they maintain? Silly, I know.
06-05-2014 08:00 AM
"I have not yet been able to figure out how to make this work with the Vivado logic analyzer tools. I fear that XVC support may have been dropped in Vivado. Is there any chance this interface will be supported?"
We are currently working on XVC support for Vivado.
"I would like to know if Xilinx plans to publish their TCF protocol extensions so that users can develop interoperable implementations of the hardware server. "
What types of use cases are you working on?
06-19-2014 09:42 AM
Does anyone know if XVC support has been added to Vivado 2014.2?
The board I've designed has a microcontroller with a network interface (100BASE-T) and it supports TCP/IP. If I can make this micro appear as an XVC "server" that would allow me to connect to the JTAG chain remotely and use Vivado/ISE/Chipscope/Impact/etc. over the network.
Seems like the ideal way to remotely program Xilinx devices over the network and also use debug tools like Chipscope too.
Is the "Hardware Server" in Vivado talking XVC or some other protocol?
09-04-2014 08:25 AM
On the other hand, XVC seems to be very simple and useful to those users who just want to configure/connect to FPGAs via JTAG over TCP/IP. Hopefully the Vivado hardware manager will support XVC soon.
10-24-2014 07:53 AM
Any updates on XVC support Vivado 2014.3? I've got it installed and have been poking around in the Hardware Manager, but don't see any references to XVC.
10-30-2014 12:40 PM
11-10-2014 01:49 PM
Thanks Duth! We're working on implementing the XVC server in our microcontroller now. As soon as we get it working I'll update this thread with what we've learned.
04-16-2015 01:35 AM
04-16-2015 03:51 PM
The Application Note is in its final review stages. We are hoping to be able to push out the application note not too far from our 2015.1 release on April 23rd. I would say a guess right now is 1 week of May. We are also working on updating the main XVC landing page as well and that will also happen when the application note goes live.
As you saw from the github, we want to make the XVC protocol more open in Vivado.
09-26-2018 09:04 AM
just like @jamieson, we think to implement hw_server + XVC on a microcontroller.
The microcontroller will have a network interface, support TCP/IP, run hw_server and has a 4 pin JTAG interface (bit-banged) using XVC
I want to know if XVC allows for the following:
1) remote JTAG programming & software (SDK) /hardware (ILA) debug of Zynq devices a over network connection (no need to open equipment)
2) have an (ultimate) tool for 'disaster' recovery : in case the FSBL or U-boot or linux image gets corrupted somehow (i.e. error during remote update), and there's no longer a network connection available through the Zynq -> the microcontroller allows to re-program the system over a network interface
I just learned from UG973 - Releaste notes Vivado 2018.1 that it supports now XVC for remote debug!
From UG908 I learned that hw_server supports several Digilent and Xilinx JTAG cables (like JTAG-HS1, JTAG-HS2, JTAG-HS3, ...)
From this github repo I learned that the 4-bit JTAG interface unfortunately does not suppport SRST or TRST, I believe this is usefull for Zynq debug ... ?
@jamieson did you get your solution working?
09-26-2018 10:07 AM
Yes, we did get XVC running on our microcontroller setup. We're using a Cortex-M3 microcontroller with 100BASE-T network interface and bit-banging the JTAG pins. Our software is based around the KEIL RTX RTOS and network extensions.
Performance over a private local network is roughly equal to a Xilinx USB JTAG cable.
None of our targets are Zynq devices so I can't speak to that. But our setup is working well for remote programming and debugging various 7 series and UltraScale FPGAs.
09-27-2018 05:41 AM - edited 09-27-2018 05:58 AM
thanks @jamieson for sharing that, we were thinking of the same processor (Cortex M3 :-)
I just read through XAPP1251, that clears up a lot of my questions :-)
Q1) Just wondering if the speed is not an issue for you (100Mbit ethernet and a bit-banged interface) ...? Since you are using UltraScale devices, I guess the speed is rather acceptable?
Q2) I've also read that XSDB (Xilinx System Debugger) can be used to debug sw apps over the XVC connection - I never used the XSDB command line, but I assume this also means I can just use SDK to download and debug/step through my applications over the XVC connection?
Q3) I don't get the phrase marked in green in the screenshot below from UG908 (programming & debug) : 'Vivado does not support any of the Vivado programming features' .... so XVC annot be used to program a bistream ? I must be reading this in a wrong way ?
fyi : for linux user space application debugging, I already used tcf_agent + remote SDK conneciton, that works great too.