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Scholar dpaul24
Scholar
9,812 Views
Registered: ‎08-07-2014

Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Hi,

 

Using Coregen I had generated an AXI Interconnect 1.06 IP which supports 1 master and 2 slaves interfaces. I have integrated it in my design.

 

But in the cycles immediately following RESETN, there is 'z' propagation on the master interface side for the RVALID signal. I can gurantee that this z is not coming from the connected slaves. The interconnect is propagating this z. This is causing errors in my top-level design.

 

The master, slaves and the interconnect all operate at the same frequency and receive the same reset.

 

Can anyone give a clue/hints as to why there is z propagation?

 

btw - The ds768_axi_interconnect.pdf spec specifies in Pg 31 that "The INTERCONNECT_ARESETN input must be held active (Low) for a minimum of 16 clock cycles to ensure complete resetting of all internal logic." I am NOT following this. I have the INTERCONNECT_ARESETN held for 4 or 5 clock cycles. Can this be a reason?

 

Please help if anyone has used this interconnect IP.

 

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Scholar dpaul24
Scholar
17,761 Views
Registered: ‎08-07-2014

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Ok, I understood where I was wrong!

 

In the axi interconnect v 1.06a using coregen, multi-master single -slave environment is available.

I thought the reverse was applicable. Hence was my confusion and errors during simulation with the top-level.

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Scholar markcurry
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Registered: ‎09-16-2009

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Double check your connections and directions.  On the Master side of the axi_interconnect, RVALID is an INPUT.  So your logic should be driving this.

 

The ports of the axi_interconnect are named from ITS point of view.

 

Regards,

 

Mark

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Scholar dpaul24
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9,766 Views
Registered: ‎08-07-2014

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Maybe I am doing something stupid, so please answer this stupid question f mine!

 

Let me take the eg of the signal AWADDR.

 

wtr to the AXI master I am having, the AWADDR is an o/p signal (it generates read and write addresses).

I want to connect this single master to the AXI Interconnect matrix generated by Coregen. So I expect the M00_AXI_AWADDR signal on the interconnect to be of nature input.

But in the generated AXI interconnect, I see the signal M00_AXI_AWADDR of nature output.

 

I have the understanding that the AWADDR output signal from my AXI Master IP block needs to be connected to the M00_AXI_AWADDR signal on the AXI Interconnect. The AXI Interconnect will then route it to the slaves.

 

Please clarify!

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Scholar dpaul24
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17,762 Views
Registered: ‎08-07-2014

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Ok, I understood where I was wrong!

 

In the axi interconnect v 1.06a using coregen, multi-master single -slave environment is available.

I thought the reverse was applicable. Hence was my confusion and errors during simulation with the top-level.

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Scholar markcurry
Scholar
9,742 Views
Registered: ‎09-16-2009

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Glad you figured out.

 

As to the Private Mail you sent me - post the question here if it's still relevant, or in a new thread.  I don't respond to PMs...

 

Regards,

 

Mark

 

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Scholar dpaul24
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9,715 Views
Registered: ‎08-07-2014

Re: Xilinx AXI Interconnect 1.06 IP propagates 'z' during the initial cycles immediately after reset

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Fair enough!
Let me try to implement it first by myself. If I hit a brick-wall I'll create a new thread.

Thanks & regards,
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