UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor shultzam
Visitor
9,454 Views
Registered: ‎07-20-2015

Zynq ZC706 EMIO-GPIO Interface

Hello,

 

I'm very new to the Zynq boards, and I have a ZC706 and trying to familiarize myself with it. Basically I want to start adding functionality to pushbuttons and LEDs for now. I see that none of the LEDs are connected to an MIO pin when I look at the schematic. My question is how do I program the PL to make the connection between the EMIO and the FPGA in order to simply blink an LED?

 

Thanks.

0 Kudos
2 Replies
Teacher muzaffer
Teacher
9,332 Views
Registered: ‎03-31-2012

Re: Zynq ZC706 EMIO-GPIO Interface

create a default project for your board which will add the necessary ip (called axi-gpio) to the pl and connect LEDs to it. After that you can write a program to talk to axi-gpio and blink the leds.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Visitor shultzam
Visitor
9,303 Views
Registered: ‎07-20-2015

Re: Zynq ZC706 EMIO-GPIO Interface

Hello muzaffer,

 

Thanks, I understand what's going on now better than I have the past few days - but I'm still missing something here. I have simple code in VHDL to connect the behavior of my push buttons to my LEDs, but nothing happens when the bitstream is sent to the board.

 

I have added the LEDs and push buttons to the axi-gpio.. and I've included an image if you'd like to ensure it is done correctly. But what I think is happening is that my variable in VHDL are not mapped to axi-gpio. Any way you could help me out with that aspect?

 

Other possible issues:

1) My constraints are empty, which is not something I'm used to after working with ISE.

2) My VHDL file is listed under "Unreferenced" in the Block Design/Libraries view.

3) My VHDL file is attached as well if you'd like to examine it for issues.

axi_gpio.png
0 Kudos