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Visitor
Visitor
8,907 Views
Registered: ‎01-26-2013

about the usage of resize function

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

 

use IEEE.numeric_std.ALL;

 

 

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

 

entity project1 is

port(a:in STD_LOGIC_vector(23 downto 0);

     b:in STD_LOGIC_vector(23 downto 0);

     z:out STD_LOGIC_vector(24 downto 0));

end project1;

 

architecture Behavioral of project1 is

 

begin

 

 z<= (resize(a,25))+(resize(b,25));

 

 

 

end Behavioral;

 

 

The error i got is

 

ERROR:HDLParsers:808 - "D:/projects final/signextension/project1.vhd" Line 43. resize can not have such operands in this context.

ERROR:HDLParsers:808 - "D:/projects final/signextension/project1.vhd" Line 43. resize can not have such operands in this context.

 

Process "Check Syntax" failed

 

can you solve the problem in the code which i have mentioned above?

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5 Replies
Highlighted
Teacher
Teacher
8,902 Views
Registered: ‎11-14-2011

Re: about the usage of resize function

I'm taking a bit of guess that the problem lies with your use of libraries. You have named std_logic_arith, std_logic_signed and numeric_std. You shouldn't really mix them.

 

Just pick numeric_std (as it is the official library) and use that.

 

If you do, you will see (by reading the library functions for resize) that the input argument must be either signed or unsigned, not std_logic_vector.

 

You can either define your signals as signed/unsigned as appropriate or recast before resizing.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
Highlighted
Historian
Historian
8,890 Views
Registered: ‎02-25-2008

Re: about the usage of resize function

a) don't use std_logic_arith ever.

b) resize() is in the numeric_std package and works on unsigned and signed.

----------------------------Yes, I do this for a living.
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Highlighted
Visitor
Visitor
8,879 Views
Registered: ‎01-26-2013

Re: about the usage of resize function

Can you correct the code which i have posted it to you?

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Highlighted
Visitor
Visitor
8,878 Views
Registered: ‎01-26-2013

Re: about the usage of resize function


Can you correct the code which i have posted it to you?
.
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Highlighted
Teacher
Teacher
8,873 Views
Registered: ‎11-14-2011

Re: about the usage of resize function

Are you serious? Really, you couldn't do it yourself from the comments that have been made?

 

OK then, just this once, assuming you want to use signed vectors ...

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity project1 is
 
port(a:in STD_LOGIC_vector(23 downto 0);
     b:in STD_LOGIC_vector(23 downto 0);
     z:out STD_LOGIC_vector(24 downto 0));
end project1;
 
architecture Behavioral of project1 is

  signal a_int, b_int : signed(23 downto 0);
  signal z_int        : signed(24 downto 0);
  
begin

 a_int <= signed(a);
 b_int <= signed(b); 
 z_int <= (resize(a_int,25))+(resize(b_int,25));
 z     <= std_logic_vector(z_int);
 
end Behavioral;

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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