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Visitor
Visitor
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Registered: ‎12-07-2014

accessing multiple elements in array at the same time vhdl

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how can i access four elements from a 2d array or array of array in one process at the same time? in this sample, i am trying to access intg1 at the same time, the synthesis is taking for ever.

tempo
:= to_integer(unsigned('0' & img1(i1_1,j1_1))); if i1_1-1>=0 then tempo:=intg1(i1_1-1)(j1_1)+tempo; end if; if j1_1-1>=0 then tempo:=intg1(i1_1)(j1_1-1)+tempo; end if; if i1_1-1>=0 and j1_1-1>=0 then tempo:=tempo-intg1(i1_1-1)(j1_1-1); end if;
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Professor
Professor
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Registered: ‎08-14-2007

Re: accessing multiple elements in array at the same time vhdl

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Is this inside a clocked process?

 

If your arrays are large, the tools will try to use block RAM.  However they can't do that if you don't allow at least one clock cycle for read access.  Accessing more than 2 elements in the same array on the same clock cycle will either cause the tools to replicate the BRAM so you have more read ports, or if the tools can't figure that out they will instead build the array from loose flip-flops.  This would indeed cause long synthesis time if the array is large.  You should get some "info" or "warning" messages if an array cannot be implemented using a memory structure.  If you think the array should be able to be implemented in a pair of BRAMs (to get 4 read ports) then you might need to help the tools find that solution by changing your coding to more closely match a BRAM inference template.  In any case, I'd suggest looking at the reports to see if this is your issue (building the array from fabric registers).

-- Gabor

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Professor
Professor
12,833 Views
Registered: ‎08-14-2007

Re: accessing multiple elements in array at the same time vhdl

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Is this inside a clocked process?

 

If your arrays are large, the tools will try to use block RAM.  However they can't do that if you don't allow at least one clock cycle for read access.  Accessing more than 2 elements in the same array on the same clock cycle will either cause the tools to replicate the BRAM so you have more read ports, or if the tools can't figure that out they will instead build the array from loose flip-flops.  This would indeed cause long synthesis time if the array is large.  You should get some "info" or "warning" messages if an array cannot be implemented using a memory structure.  If you think the array should be able to be implemented in a pair of BRAMs (to get 4 read ports) then you might need to help the tools find that solution by changing your coding to more closely match a BRAM inference template.  In any case, I'd suggest looking at the reports to see if this is your issue (building the array from fabric registers).

-- Gabor

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: accessing multiple elements in array at the same time vhdl

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depends on how your memory layout is designed/implemented. If your array is small, everything can be in registers so you can read any/all of them in parallel. If you store your data in block rams, you can use multiple block rams in parallel (4 wide?) and you can read 4 values for every clock cycle/input index. You need to make sure that the 4 values you need every cycle are available in parallel. Drawing a memory allocation diagram helps.
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