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Explorer
Explorer
7,313 Views
Registered: ‎08-23-2011

apply false path to input port of submodule ...

hi,

 

i was wondering if i can apply falsepath to input port of a submodule?

 

the design heir is something like - top_level/mod1/mod2/input1 where input1 is the input pin on the submodule on whic i want to set a false path - so that all regs/wires connected to input1 are removed from timing analysis.

 

so is it enough to simply specify the following in the UCF 

NET "mod1/mod2/input1" TIG;         ....... i am actually doing this but its always flagged as an error

 

is there some restriction that TIG can only be applied on clocked elemets  or clock pins (i.e. a register driven by input1 port) but cannot be applied on input1 (or output pin of a submodule) directly???

 

please let me know ...

 

z.

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3 Replies
Xilinx Employee
Xilinx Employee
7,237 Views
Registered: ‎04-16-2012

Re: apply false path to input port of submodule ...

Hello,

Can you try creating using constarint wizard in ISE.

See page no. 94 in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ise_tutorial_ug695.pdf

Thanks,
Vinay

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Xilinx Employee
Xilinx Employee
7,232 Views
Registered: ‎07-21-2014

Re: apply false path to input port of submodule ...

Hi,

Please refer following AR on how to apply TIG.
http://www.xilinx.com/support/answers/10025.html

Thanks,
Shreyas
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Explorer
Explorer
7,202 Views
Registered: ‎08-23-2011

Re: apply false path to input port of submodule ...

hi,

 

can you please clarify something - 

 

when i apply false path constraint to the design, does it actually change the way the design is routed or does it only tell the ISE tool that the path specified need not be analysed during timing, without any impact to the way the net is placed and routed?

 

z.

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