05-22-2015 11:23 PM
i was wondering if i can apply falsepath to input port of a submodule?
the design heir is something like - top_level/mod1/mod2/input1 where input1 is the input pin on the submodule on whic i want to set a false path - so that all regs/wires connected to input1 are removed from timing analysis.
so is it enough to simply specify the following in the UCF
NET "mod1/mod2/input1" TIG; ....... i am actually doing this but its always flagged as an error
is there some restriction that TIG can only be applied on clocked elemets or clock pins (i.e. a register driven by input1 port) but cannot be applied on input1 (or output pin of a submodule) directly???
please let me know ...
05-25-2015 04:20 AM - edited 05-25-2015 04:22 AM
Can you try creating using constarint wizard in ISE.
See page no. 94 in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ise_tutorial_ug695.pdf
05-25-2015 04:26 AM
05-26-2015 10:16 AM
can you please clarify something -
when i apply false path constraint to the design, does it actually change the way the design is routed or does it only tell the ISE tool that the path specified need not be analysed during timing, without any impact to the way the net is placed and routed?