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Visitor zozulak
Visitor
32,196 Views
Registered: ‎12-05-2007

binary multiplication in vhdl

hi,
I am having problem with simulink, when simulationg a test bench concerning binary multiplication in vhdl.
 
the code for the code is this one:
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity vmul8x8i is
port (
X: in UNSIGNED (7 downto 0);
Y: in UNSIGNED (7 downto 0);
P: out UNSIGNED (15 downto 0)
);
end vmul8x8i;
architecture vmul8x8i_arch of vmul8x8i is
begin
P <= X * Y;
end vmul8x8i_arch;
 
 
and for the test bench is:
 

-- VHDL Test Bench Created from source file vmul8x8i.vhd -- 22:46:03 12/04/2007
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY vmul8x8i_mul_t_vhd_tb IS
END vmul8x8i_mul_t_vhd_tb;
ARCHITECTURE behavior OF vmul8x8i_mul_t_vhd_tb IS
 COMPONENT vmul8x8i
 PORT(
  X : IN std_logic_vector(7 downto 0);
  Y : IN std_logic_vector(7 downto 0);         
  P : OUT std_logic_vector(15 downto 0)
  );
 END COMPONENT;
 SIGNAL X :  std_logic_vector(7 downto 0);
 SIGNAL Y :  std_logic_vector(7 downto 0);
 SIGNAL P :  std_logic_vector(15 downto 0);
BEGIN
 uut: vmul8x8i PORT MAP(
  X => X,
  Y => Y,
  P => P
 );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
   X <= "00000001";
   Y <= "00000010";
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
and the error reported is:
 
types do not match for port X.
 
can anybody tell me  the reason of this.
 
thanks,
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4 Replies
Explorer
Explorer
32,149 Views
Registered: ‎08-30-2007

Re: binary multiplication in vhdl


Hello....

The problem is that the entity declaration of the vmul8x8i component uses the UNSIGNED type for the ports while the testbench uses std_logic_vector type (this is also noted at the auto-generated testbench) and also that you use the std_logic_arith package.

The best way is to use everywhere std_logic_vector type and the std_logic_unsigned package. This package contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED. This is also a simple way of allowing data of type STD_LOGIC_VECTOR to participate directly in arithmetic operations.

Alternatively you can use everywhere the unsigned type.

Hope that helps....

George


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Visitor zozulak
Visitor
32,146 Views
Registered: ‎12-05-2007

Re: binary multiplication in vhdl

Hi George,
 
Thanks a lot for the answer. I adopted your solution and now the simulations runs as expected.
 
Ivan
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Explorer
Explorer
32,029 Views
Registered: ‎08-14-2007

Re: binary multiplication in vhdl

Despite the naming, std_logic_arith and std_logic_unsigned aren't actually standard packages.  While I won't argue with a working solution, if you ever need to combine the use of signed and unsigned arithmetic in a system, they can lead to problems, so for larger systems I'd recommend sticking to IEEE.numeric_std.  Using numeric_std does mean that you'll sometimes need to code explicit type casts between std_logic_vector, unsigned, and signed types, but IMHO that's a fairly small price to pay.
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8,638 Views
Registered: ‎03-01-2014

Re: binary multiplication in vhdl

Hi, I need structure model code for 8-bit muliplier using conventional method. Can anyone help me out of this?

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