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kkchia_keyasic
Visitor
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Registered: ‎12-18-2007

black box been optimized away

Hi,

 

I have design synthesized at synplifypro. The edf file and port list file are then moved to the ISE as a black box to synthesized with other HDL design. My problem is the design of black box is optimized away by ISE and at the PnR only other IP is routed. When I have other IP commented and IO of the black box connected as the IO pad, I got only 25  track routed. It seems to me the ISE somehow interpret that the design of black box is useless and remove the whole design. How can I makesure the ISE will implement my design in black box?

 thanks.

 

KK 

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sridar
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Registered: ‎09-20-2007

Make sure that component is instantiated correctly and ports are mapped correctly.

Also be sure that ports mapped to the componenets are not left unconnected.

FPGA freak
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kkchia_keyasic
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Registered: ‎12-18-2007

This is the port list of the black box:

 

module    FPGA_PCIETop
    (                            
                   
    PCIRST_tb2,
    PCLK_IN,
    TxData_Ln0,
    TxDataK_Ln0,
    RxPolarity_Ln0,
    TxDetectRx,
    TxElecIdle,
    TxCompliance_Ln0,
    PhyResetB,
    PowerDown,
    RxData_Ln0,
    RxDataK_Ln0,
    RxValid_Ln0,
    PhyStatus,
    RxElecIdle_Ln0,
    RxStatus_Ln0,
        pipe_rate,
    pipe_txdeemph,
    pipe_txmargin,
    pipe_txswing,
    PCLK_half_buf   //Nathan 29sept 09
   
    );


input             PCIRST_tb2;
input            PCLK_IN;
input            PCLK_half_buf; //Nathan 29sept 09
output  [15:0]          TxData_Ln0;   
output  [1:0]           TxDataK_Ln0;  
output                  RxPolarity_Ln0;
output                  TxDetectRx;  
output                  TxElecIdle;      
output                  TxCompliance_Ln0;
output                  PhyResetB; 
output  [1:0]           PowerDown;             
input   [15:0]          RxData_Ln0;            
input   [1:0]           RxDataK_Ln0;           

 

input                   RxValid_Ln0;           
input                   PhyStatus;             
input                   RxElecIdle_Ln0;        
input   [2:0]           RxStatus_Ln0;
//output            PCLK_2X_bufg;
output                  pipe_rate;
output                pipe_txdeemph;  
output  [2:0]        pipe_txmargin;  
output              pipe_txswing;   

endmodule
 

Below is the top level file, I have removed some IP instantiation to shorten the code to be shown here:

 

module KA_PCIETop(refclk_p, refclk_n, mperst, rxp, rxn, txp, txn, wake,

        phystatus, powerdown, txdetectrx, txdata0, txdatak0, txelecidle, txcompl, rxpolarity, rxdata0, rxdatak0, rxvalid, rxelecidle, rxstatus0, rate, clk125, clk250);


   input         refclk_p;

   input         refclk_n;

   input         mperst;

   input         rxp;

   input         rxn;

   inout         txp;

   inout         txn;

   output        wake;

    input [15:0]   rxdata0;

   input [1:0]    rxdatak0;

   input [2:0]    rxstatus0;

   input [0:0]    rxvalid;

   input [0:0]    rxelecidle;

   input          phystatus;

   

    output [1:0]    powerdown;

   output          txdetectrx;

   output [15:0]   txdata0; 

   output [1:0]    txdatak0;

   output [0:0]    txelecidle;

   output [0:0]    txcompl;

   output [0:0]    rxpolarity;

    output rate;

    input clk125;

    input clk250;


   wire          clk;

   wire          clk125;

   wire          clk250;

   reg           rstn;

   reg           rstn_i;

   wire          rstn_srst_out;

   reg [19:0]    rstn_cnt;

   wire [63:0]   ZERO;

   wire          refclk_out;

  

   reg [11:0]    clk_10khz_cnt;

   reg           clk_10khz;

   wire          clkmux;

   reg          rate;

   reg           rate_r;


 `ifdef TWO_FPGA  

   wire [15:0]   rxdata0;

   wire [1:0]    rxdatak0;

   wire [2:0]    rxstatus0;

   wire [0:0]    rxvalid;

   wire [0:0]    rxelecidle;

   wire          phystatus;

   

    reg [1:0]    powerdown;

   reg          txdetectrx;

   reg [15:0]   txdata0; 

   reg [1:0]    txdatak0;

   reg [0:0]    txelecidle;

   reg [0:0]    txcompl;

   reg [0:0]    rxpolarity;

`else

   wire [15:0]   rxdata0;

   wire [1:0]    rxdatak0;

   wire [2:0]    rxstatus0;

   wire [0:0]    rxvalid;

   wire [0:0]    rxelecidle;

   wire          phystatus;   

   

    wire [1:0]    powerdown;

   wire          txdetectrx;

   wire [15:0]   txdata0; 

   wire [1:0]    txdatak0;

   wire [0:0]    txelecidle;

   wire [0:0]    txcompl;

   wire [0:0]    rxpolarity;

  

`endif  //TWO_FPGA  





`ifdef TWO_FPGA  

   wire [1:0]    d_powerdown;

   wire             d_txdetectrx;

   wire [15:0]    d_txdata0;

   wire [1:0]    d_txdatak0;

   wire [0:0]    d_txelecidle;

   wire [0:0]    d_txcompl;

   wire [0:0]    d_rxpolarity;

   wire             d_rate;

   reg [15:0]    d_rxdata0;

   reg [1:0]     d_rxdatak0;

   reg [0:0]    d_rxvalid;

   reg [0:0]    d_rxelecidle;

   reg [2:0]     d_rxstatus0;

   reg            d_phystatus;

`endif //TWO_FPGA

  //------------------------------------------------

  //

  //    KA PCIE core

  //------------------------------------------------

`ifdef TWO_FPGA  

   //-----------------------------------------------

   // pipeline pipe signal

   //-----------------------------------------------

   always @(posedge clk or negedge rstn)

   begin

       if(!rstn)

       begin

       powerdown        <='b0;

        txdetectrx    <='b0;

        txdata0        <='b0;

        txdatak0        <='b0;

        txelecidle[0]<='b0;

        txcompl[0]    <='b0;

        rxpolarity[0]<='b0;

        rate            <='b0;

       

        d_rxdata0            <='b0;

        d_rxdatak0            <='b0;

        d_rxvalid[0]        <='b0;

        d_rxelecidle[0]    <='b0;

        d_rxstatus0        <='b0;

        d_phystatus        <='b0;

       end

      

       else

           begin

          

       powerdown        <= d_powerdown;

        txdetectrx    <= d_txdetectrx;

        txdata0        <= d_txdata0;

        txdatak0        <= d_txdatak0;

        txelecidle[0]<= d_txelecidle[0];

        txcompl[0]    <= d_txcompl[0];

        rxpolarity[0]<= d_rxpolarity[0];

        rate            <= d_rate;

          

       d_rxdata0            <=    rxdata0;  

        d_rxdatak0            <=    rxdatak0; 

        d_rxvalid[0]        <=    rxvalid[0];  

        d_rxelecidle[0]    <=    rxelecidle[0];

        d_rxstatus0        <=    rxstatus0;

        d_phystatus        <=    phystatus;

          

           end

   end

  

`endif     //TWO_FPGA        
BUFGMUX mux_clk(

      .O(clk),

      .I0(clk125),

      .I1(clk250),

      .S(clkmux)

   );
       

  FPGA_PCIETop u_KABB                //synthesis attribute box_type FPGA_PCIETop "black_box"

    (                                            

    .PCIRST_tb2            (rstn),

    .PCLK_IN                (clk),

    .TxData_Ln0            (d_txdata0),           

    .TxDataK_Ln0        (d_txdatak0),          

    .RxPolarity_Ln0    (d_rxpolarity[0]),     

    .TxDetectRx            (d_txdetectrx),        

    .TxElecIdle            (d_txelecidle[0]),     

    .TxCompliance_Ln0    (d_txcompl[0]),        

    .PhyResetB            (),                  

    .PowerDown            (d_powerdown),

    .RxData_Ln0            (d_rxdata0),

    .RxDataK_Ln0        (d_rxdatak0),          

    .RxValid_Ln0        (d_rxvalid[0]),        

    .PhyStatus            (d_phystatus),         

    .RxElecIdle_Ln0    (d_rxelecidle[0]),     

    .RxStatus_Ln0        (d_rxstatus0),         

    .pipe_rate            (d_rate),              

    .pipe_txdeemph        (),

    .pipe_txmargin        (),

    .pipe_txswing        (),

    .PCLK_half_buf        (clk_div2) 

   

//other IP instantian is removed 

endmodule

 

 

As I have mentioned in my last message, the black box IO is added as top level IO pad to ensure the ISE keep the design. But apparently it doesnt help.

Anyone has any idea whats go wrong?

 

KK

 

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