I am using Xilinx Virtex 5 (XC5VLX110T) FPGA to prototype a custom processor. As I have to go through several iterations to test different applications, I though I could use data2mem application to simply merge my application within the FPGA bitstream. However, I encounter a couple of problems creating the bmm file.
My processor has 3 memories (one program memory and 2 data memories). In VHDL, I have the following code for each memory (just changed pmem by x or ymem):
type pmem_core is array(0 to size - 1) of bit_vector(g_data_width - 1 downto 0); impure function pmem_load (pmem_ext_load : in string) return pmem_core is file pmem_file : text is in pmem_ext_load; variable pmem_line : line; variable pram_core : pmem_core; begin for I in pmem_core'range loop readline (pmem_file, pmem_line); read (pmem_line, pram_core(I)); end loop; return pram_core; end function; signal pram_core : pmem_core := pmem_load("../memories/PMEM.txt"); signal wen_tmp : std_logic;
wen_tmp <= '1';
process (clk) begin if clk'event and clk = '1' then if (cs = '1') then case wen_tmp is when '0' => pram_core(conv_integer(a(11 downto 0))) <= to_bitvector(d); when '1' => q <= to_stdlogicvector(pram_core(conv_integer(a(11 downto 0)))); when others => null; end case; end if; end if; end process;
I used the FPGA Editor (ISE 11.1) after P&R to determine type and location for the BRAMs used. And then I constructed my bmm file, that looks like this: ADDRESS_SPACE pmem RAMB36 [0x0000:0x47ff] BUS_BLOCK proc/i_pmem_wrapper/pram_core_pram_core_0_0/RAMB36_EXP [7:0] PLACED = X2Y8; proc/i_pmem_wrapper/pram_core_pram_core_0_1/RAMB36_EXP [15:8] PLACED = X2Y7; proc/i_pmem_wrapper/pram_core_pram_core_0_2/RAMB36_EXP [23:16] PLACED = X2Y6; proc/i_pmem_wrapper/pram_core_pram_core_0_3/RAMB36_EXP [31:24] PLACED = X2Y5; END_BUS_BLOCK; END_ADDRESS_SPACE;
Executing data2mem with the following command, given the following error: data2mem -bm proc.bmm -bt proc.bit -d > proc.txt ERROR data2MEM:26 - Illegal bit lane width in ADDRESS_SPACE 'pmem'. 'proc/i_pmem_wrapper/pram_core_pram_core_0_0/RAMB36_EXP [7:0]' is 8 bits wide. Only 1, 2, 4, 9, 18, 36, 72 bit widths are allowed for this device.
I do not understand why I cannot use 8 bits wide, because in FPGA Editor I can see that: - pram_core_pram_core_0_0 pins: pmem_q(0) until pmem_q(7), - pram_core_pram_core_0_1 pins: pmem_q(8) until pmem_q(15), - pram_core_pram_core_0_2 pins: pmem_q(16) until pmem_q(23), - pram_core_pram_core_0_3 pins: pmem_q(24) until pmem_q(32)
Can anyone tell me what is wrong with my bmm file? I really have no clue.