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Visitor sanjay.patil
Registered: ‎02-09-2012

buffering and switching inside fpga



I'm are receiving packets of random length and in random order  continueously at one frequency and I want to buffer and output them in sequence at same/difference frequency.


Normal FIFO will not work, as packet is not going to be "first in first out" and what should be the buffer size?


Any clues?


Thanks in advance


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Teacher eilert
Registered: ‎08-14-2007

Re: buffering and switching inside fpga

Hi Sanjay,

seems like you need some sequential controller and a generously sized RAM.

You mentioned a lot of things that appear randomly, but what are the constraints that can be used to determine the ammount of memory and computing complexity?

e.g is the number of packets limited in some way (like you have a dataframe consisting of N packets)


There mist be some limitation, otherwise you need infinite ammouts of memory and time to collect packets before you can sort them sequentially.


Also, it is important to know how the packet size is determined.

Is that information in some packet header or do you have to wait for some EndOfPacket indicator?


In the worst case you have to use some processor and create a software solution which will also be more flexible to later changes of some specification details.


Have a nice synthesis


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