08-26-2012 05:32 PM
I want to design a bus extension module with combinational circuit and no control signal needed. So I want to know how can I store a signal with a very short time in a combinational circuit.
Looking forward your reply. Thank you.
08-26-2012 05:53 PM
You've given us very little to go on, and some contradictory statements. Combinational logic
by definition does not store values. You need sequential logic for storage, whether you
mean synchronous or asynchronous sequential logic.
In a sense wires store values "for a very short time" if you look at them as delay elements.
In any case it's not clear what kind of bus you're extending, and what you hope to gain by
using combinational logic.
08-26-2012 06:29 PM
08-26-2012 06:36 PM
Do you have any additional signal (i.e. a write enable) that indicates that one of the input channels has new data? If so, the design will be a pretty simple four input combinatorial multiplexer. There's no real need to store signals in order to examine them in this case, though there are some reasons why you might want to. You'll need to decide which of the channels has priority in case they all try to write at the same time. Do you care about notifying the data sources if the multiplexer is ready to accept values from them or not?
Or do you need to wait until the data changes in order to act on it? If so, what if an input channel has the same data value for more than one clock cycle? Or if it returns to zero after each word, how do you transmit all zeros?
08-26-2012 06:52 PM
08-26-2012 07:02 PM
I don't think there's any sane way to do that on an FPGA using only combinatorial logic.
Use a clocked process to store the input data on each clock cycle, and if any of them change from one cycle to the next, set the output to that (you will need to assign some priority).
If you can't tolerate the clock cycle latency, have a think about how you would construct the circuit you want using discrete logic elements.
08-27-2012 08:09 AM
Just so it's clear what you're trying to accomplish, you want something that works like:
if (input1'event) then output <= input 1;
elsif (input2'event) then output <= input 2;
elsif (input3'event) then output <= input 3;
elsif (input4'event) then output <= input 4;
Clearly the above won't synthesize, but is that basically what you're trying to accomplish?
08-27-2012 07:45 PM
I have post my code in the attachment. It failed when I synthesis the project. I don't know how to solve it.
* HDL Analysis *
Analyzing generic Entity <module4to1> in library <work> (Architecture <behavioral>).
DWIDTH = 8
INTERNAL_ERROR: Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Process "Synthesize - XST" failed
08-27-2012 08:04 PM
I am going to paraphrase what some others have said...
What you are trying to do is simply impossible.
When you synthesize code, you are trying to map a behavioral description of some hardware into real hardware on the FPGA. There is no hardware resource (certainly none in an FPGA) that can implement the functionality you are describing here - its not even close.
In an FPGA, we have pure combinatorial logic (gates), flip-flops, and latches. That's it. What you are describing is none of those, and hence it cannot be mapped into an FPGA.
The code is so far off what a synthesis tool can handle, it simply encountered a Fatal error. While the tools should never fatal (and if you want, you could file a webcase on it), but the only thing Xilinx would do is ensure that the tool generates a real "This is not synthesizable code" error, and exit.
Again, what you are trying to do here is impossible - no amount of coding is going to change that.
Perhaps if you describe the larger problem - why you think you need something that behaves like this, how it fits into a larger system - then maybe people on the forum could give you an idea as to how to re-design what you are trying to do in such a way that it will map to actual hardware.
08-28-2012 06:17 AM
First, let me repeat that what you want to do requires sequential logic by definition. "Combinational"
logic only depends on the current state of its inputs. What you are describing (without a clock) is
known as "asynchronous sequential logic" which does not map well into an FPGA.
The code you posted actually does about half of what you ask. Since it only looks at rising edges,
it won't switch inputs if some bits go low but no other bits go high at the same time. You'd need to
double the logic to include falling edges to check for any change of input.
The real question is what you're trying to accomplish. How much propagation delay can you
live with? With a clocked system running at or near the maximum clock rates of a Spartan 6
you could probably do this in synchronous logic and get only about 15 nanoseconds of delay
through the system.
The other way is to have two flip-flops per input bit, one clocked on the rising edge of the bit
and the other clocked on its falling edge. (This is already a nightmare in routing in the FPGA
which doesn't like to connect local signals to a lip-flop's clock input). Every flip-flop's D input
is tied high. Each flip-flop is then reset by the OR of all flip-flops corresponding to the other
input words. The select for each input word is then the OR of all of its flip-flops. As I already
said, this is very messy in an FPGA (but you might get it to work). It's also not clear whether
it would actually reduce the propagation delay over the synchronous system.