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Observer arunjadhav
Observer
5,689 Views
Registered: ‎02-17-2014

chipscope analyser issues

Hello every one,

 

   I am using Virtex - 5 LX330T fpga and i have used around 88% of my DSP slices.

 Now there are few particular signals when i try to monitor them i get a error message stating that ia m falling short of DSP slices but Chipscope monitoring should only effect my BRAM cells not DSP slices.

can anyone please help me out to find some alternative or the reason for it.

       

Regards,

Arun jadhav.

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5 Replies
Community Manager
Community Manager
5,685 Views
Registered: ‎06-14-2012

Re: chipscope analyser issues

To work around the issue of too many DSP being inferred, reduce the DSP utilization ratio to < 100. 

This option can be found in the XST options within Project Navigator, or it can be changed from the command line by setting the "-dsp_utilization_ratio <integer>" switch

Xilinx Employee
Xilinx Employee
5,681 Views
Registered: ‎01-03-2008

Re: chipscope analyser issues

> can anyone please help me out to find some alternative or the reason for it.

 

In the design with ChipScope, parts of your design that are inferring are likely being removed as the outputs are not used and when you insert ChipScope in the design the outputs are now connected and the inferred DSP48 are no longer removed.

------Have you tried typing your question into Google? If not you should before posting.
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Observer arunjadhav
Observer
5,651 Views
Registered: ‎02-17-2014

Re: chipscope analyser issues

Hello sir,

  Thank you for your reply, To be specific i was trying to moniter the fifo read enable signals and that was getting connected to other fifo write enable but i dont find any purpose of DSP slice requirement there in that context.

 

Regards,

Arun jadhav

 

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Xilinx Employee
Xilinx Employee
5,648 Views
Registered: ‎01-03-2008

Re: chipscope analyser issues

I would suggest that you examine the synthesis and map report files for the two designs to see if there is a difference in the trimming information that may provide an answer.
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5,622 Views
Registered: ‎02-28-2011

Re: chipscope analyser issues

In our old Spartan 3 devices I remember similar issues. Some BRAM and DSP block shared routing resources and that prevented the use of some of them.

If you add Chipscope it will use up BRAM which might not be able to be used becuase the routing is already used up by your DSP blocks. You might be able to free a few of those by changing the multiplier implementation to Behavioral on a few DSPs.

 

Regards Markus

 

 

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