03-12-2014 07:52 AM
Hello every one,
I am using Virtex - 5 LX330T fpga and i have used around 88% of my DSP slices.
Now there are few particular signals when i try to monitor them i get a error message stating that ia m falling short of DSP slices but Chipscope monitoring should only effect my BRAM cells not DSP slices.
can anyone please help me out to find some alternative or the reason for it.
03-12-2014 08:06 AM
To work around the issue of too many DSP being inferred, reduce the DSP utilization ratio to < 100.
This option can be found in the XST options within Project Navigator, or it can be changed from the command line by setting the "-dsp_utilization_ratio <integer>" switch
03-12-2014 08:11 AM - edited 03-12-2014 08:11 AM
> can anyone please help me out to find some alternative or the reason for it.
In the design with ChipScope, parts of your design that are inferring are likely being removed as the outputs are not used and when you insert ChipScope in the design the outputs are now connected and the inferred DSP48 are no longer removed.
03-12-2014 09:00 PM
Thank you for your reply, To be specific i was trying to moniter the fifo read enable signals and that was getting connected to other fifo write enable but i dont find any purpose of DSP slice requirement there in that context.
03-12-2014 09:19 PM
03-13-2014 03:06 PM
In our old Spartan 3 devices I remember similar issues. Some BRAM and DSP block shared routing resources and that prevented the use of some of them.
If you add Chipscope it will use up BRAM which might not be able to be used becuase the routing is already used up by your DSP blocks. You might be able to free a few of those by changing the multiplier implementation to Behavioral on a few DSPs.