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Explorer
Explorer
10,424 Views
Registered: ‎08-23-2011

clock constraints and bi-dir IOs ... general questions ...

hi,

 

i had some questions regarding clock constraints and  bi-dir gpios -

 

1) clock dedicated route = false - when should we use this constraint? i know the function of this constraint - if you need to place some clock pins an an IOB slice which violates clocking rules, then set this parameter to false in ucf. but other than that, what other use case will this constraint have?

 

if i have an i2c clock coming from a gpio pin and going into my design, then should i set this path to clock_dedicated_route = false specifically or should i wait to see what the tool spits out? 

 

should we use this constraint for slow/fast clocks?

 

will it help in meeting timing or disimprove it? 

 

2)this may be a bit more of a noob question - should we constraint clocks that go into our design via a gpio pin (the pin does not go into a PLL but clocks modules within the design)?

 

if the above is yes, then apart from period constraint, are there any other recommended constraints that should be used, apart from period constriant?

 

3) if there is a clock that goes out of my design via a gpio pin, then should i constrain it? if yes, only period constraint or are there any other recommended constraints?

 

4) if i declare a gpio pin as inout, and only connect it to a an output pin (or input pin) from one of the sub-modules in my design, then do i still need a tri-state buffer to handle bi-dir IO? or will xilinx reslolve it itself?

 

z.

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6 Replies
Xilinx Employee
Xilinx Employee
10,418 Views
Registered: ‎07-31-2012

Re: clock constraints and bi-dir IOs ... general questions ...

1) clock dedicated route = false - when should we use this constraint? i know the function of this constraint - if you need to place some clock pins an an IOB slice which violates clocking rules, then set this parameter to false in ucf. but other than that, what other use case will this constraint have?

 

if i have an i2c clock coming from a gpio pin and going into my design, then should i set this path to clock_dedicated_route = false specifically or should i wait to see what the tool spits out? 

 

should we use this constraint for slow/fast clocks?

 

will it help in meeting timing or disimprove it? 

A: There are certain rules which the tool imposes on the clocks to make sure that the timing is met easily for the tool and there are no violations. Not just this but other clocking rules from the user guide which if ignored may cause problems are noted. You should wait for the tool to throw these errors. YOu should not directly assign this constraint in UCF. 

 

However you should be sure that you want to give this constraint because mostly, the xilinx recommendation is to follow the clocking rules.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Xilinx Employee
Xilinx Employee
10,417 Views
Registered: ‎07-31-2012

Re: clock constraints and bi-dir IOs ... general questions ...

2)this may be a bit more of a noob question - should we constraint clocks that go into our design via a gpio pin (the pin does not go into a PLL but clocks modules within the design)?

 

if the above is yes, then apart from period constraint, are there any other recommended constraints that should be used, apart from period constriant?

 

A: yes even without a PLL or any clock manager, you SHOULD give the timing constraints. Yes PERIOD constraint should be enough for the clock. however there are other timing constraints which are needed for certain cross clock paths and for the IO's(not clock but data IO's). YOu need to check UG360 for the information on the timing..

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Xilinx Employee
Xilinx Employee
10,409 Views
Registered: ‎07-31-2012

Re: clock constraints and bi-dir IOs ... general questions ...

Hi,

 

3) if there is a clock that goes out of my design via a gpio pin, then should i constrain it? if yes, only period constraint or are there any other recommended constraints?

A: For a clock going out of the design, i dont think you need a constraint. The PERIOD constraint is only for the logic transfer between synchronous elements withing the fabric. If that clock is being used internally then that needs period constraint. If you are directly trying to output the clock, there is no use giving a PERIOD constraint. However for source synchronous interfaces between the FPGA and the connected component, you need to take care of the timing at the connected component.

 

For IO timing you need to focus more on the data pins and you would need to constraint the data pins using OFFSE_OUT with respect to the latching clock, rather than constraint the clock. Does this makes sense? Read through UG360 for clarity on the timign constraints.

 

4) if i declare a gpio pin as inout, and only connect it to a an output pin (or input pin) from one of the sub-modules in my design, then do i still need a tri-state buffer to handle bi-dir IO? or will xilinx reslolve it itself?

A:You would need a tri-state buffer. Check the library guide for the tristate buffer module. However before that i would recommend you to implement this and check what does the tool infer. However it is safer to instantiate.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Moderator
Moderator
10,400 Views
Registered: ‎01-16-2013

Re: clock constraints and bi-dir IOs ... general questions ...

Hi,

Regarding Q.1 I will suggest try to avoid as much as possible to use clock dedicated route = false constraints. Try to achieve valid clocking structure. If in case it's impossible to use dedicated clock routing then you can use this constraints.

There are draw backs of this clock dedicated route = false constraints. PVT variation affects more results in clock skew.

Thanks,
Yash
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Xilinx Employee
Xilinx Employee
10,273 Views
Registered: ‎07-31-2012

Re: clock constraints and bi-dir IOs ... general questions ...

Hi @zubin_kumar31 


Please close this thread as "Accept as Solution" in case it helped.


Thanks,
Anirudh

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Historian
Historian
10,260 Views
Registered: ‎02-25-2008

Re: clock constraints and bi-dir IOs ... general questions ...


@zubin_kumar31 wrote:

hi,

i had some questions regarding clock constraints and  bi-dir gpios -

1) clock dedicated route = false - when should we use this constraint? i know the function of this constraint - if you need to place some clock pins an an IOB slice which violates clocking rules, then set this parameter to false in ucf. but other than that, what other use case will this constraint have?


You use it when you (inadvertenly, usually, but on rare occasions deliberately) put a clock input signal onto a non-clock-capable/global clock input pin. But be warned. If you do that, there are no guarantees that you'll meet input setup and hold requirements.

 

In other words, it is to be avoided as much as possible.


if i have an i2c clock coming from a gpio pin and going into my design, then should i set this path to clock_dedicated_route = false specifically or should i wait to see what the tool spits out? 


Pro Tip: the I2C clock signal SCL really isn't a clock in the standard usage. What you should do is bring it in on any pin you wish, and oversample it with your system clock to find the edge.


should we use this constraint for slow/fast clocks?


What is a "slow" or "fast" clock?

Whatever. That constraint is only used as described above.


will it help in meeting timing or disimprove it?


It helps the router complete its job when you screw up the PCB layout, but in general you won't meet some timing.


2)this may be a bit more of a noob question - should we constraint clocks that go into our design via a gpio pin (the pin does not go into a PLL but clocks modules within the design)?


Clocks must always be constrained. Generally, you place a PERIOD constraint on the clock input. If that clock feeds a PLL or DLL, the tools with create constraints for the clocks generated by those resources.


if the above is yes, then apart from period constraint, are there any other recommended constraints that should be used, apart from period constriant?


For inputs synchronous to those clocks, you should create an OFFSET IN constraint, to ensure that you meet setup and hold times.


3) if there is a clock that goes out of my design via a gpio pin, then should i constrain it? if yes, only period constraint or are there any other recommended constraints?


You don't. If you create a source-synchronous output bus (with various data bits synchronous to that output clock), you should create OFFSET OUT constraints on the data and the clock pin (with reference to the input clock which generates the output clock) and look for skew differences.


4) if i declare a gpio pin as inout, and only connect it to a an output pin (or input pin) from one of the sub-modules in my design, then do i still need a tri-state buffer to handle bi-dir IO? or will xilinx reslolve it itself?


The tools will probably throw a warning. Don't do that. Declare the pin as an input or an output. It's not hard to edit the file later if you decide to change it.

----------------------------Yes, I do this for a living.
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