09-17-2009 11:08 PM
How to tacckle with metastability and clock domain crossing? one possible solution is using synchronization flip flops. I want to know whether this is a suitable method if the data is not a single bit(say 40 bits)?. any body know other methods when data is large.please share ..it will be helpful
09-17-2009 11:27 PM
why not, FFs are cheap in a FPGA and all other solutions (e.g. FIFOs) may use even more ressources.
But you should consider what you are going to doo with these much signals. Are these just independent controll signals, or is it a data bus?
In the later case you don't want your data be altered by metastability-effects of the first shift register stage.
You need some controlled data flow, which can only be achieved with FIFOs.
Have a nice synthesis
09-17-2009 11:35 PM
Thanks for the reply. 40 bit data is a data bus(probably a counter value) and there is no correlation with the two clocks( any one can be high or low frequency)...you are suggesting that using a FIFO is the best method?
09-18-2009 02:51 AM - edited 09-18-2009 03:01 AM
if it is a counter value, you probably want to compare it against some constants and trigger some events.
If the counter runs with a standard binary encoding you need the FIFO to ensure the proper values.
If you use a better code scheme like gray code, where only one bit toggles at each step, you can savely use the shift register method.
If more than one bit per clock cycle is subject to change in a bus, you need FIFOs.
Have a nice synthesis
09-18-2009 07:33 AM
Do you also receive as an input the clock that is creating the 40 bit data? If so, use that
clock to load the data into a fifo, then use your internal clock to read data from the fifo.
There are other trick youcould try if you know that your internal clock is much faster than
the external data rate, but, in general, the fifo scheme is the safest & cleanest way to grab
If you get the external clock and your internal clock is much faster... Use the external clock
to grab the input data and to toggle a new_data_rdy signal. Using the faster internal clock,
double synchronize the new_data_rdy signal, then, everytime it toggles, grab the data you latched.
Note that metastibility is not the only problem. The real problem is that with non-related clocks,
you'll miss/meet setup/hold times on some signals and not others. This may or may not cause
metastability, but it will cause grabbing some data and missing other data until the next cycle.
Hope this helps!