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Anonymous
Not applicable
5,443 Views

clock domain crossing for large data

Hi

 

How to tacckle with metastability and clock domain crossing? one possible solution is using synchronization flip flops. I want to know whether this is a suitable method if the data is not a single bit(say 40 bits)?. any body know other methods when data is large.please share ..it will be helpful

 

Regards

Anjo

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5 Replies
eilert
Teacher
Teacher
5,439 Views
Registered: ‎08-14-2007

Hi Anjo,

why not, FFs are cheap in a FPGA and all other solutions (e.g. FIFOs) may use even more ressources.

But you should consider what you are going to doo with these much signals. Are these just independent controll signals, or is it a data bus?

In the later case you don't want your data be altered by metastability-effects of the first shift register stage. 

You need some controlled data flow, which can only be achieved with FIFOs.

 

Have a nice synthesis

  Eilert

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Anonymous
Not applicable
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Hi Eilert

 

Thanks for the reply. 40 bit data is a data bus(probably a counter value) and there is no correlation with the two clocks( any one can be high or low frequency)...you are suggesting that using a FIFO is the best method?

 

Regards

Anjo

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eilert
Teacher
Teacher
5,428 Views
Registered: ‎08-14-2007

Hi Anjo,

if it is a counter value, you probably want to compare it against some constants and trigger some events.

If the counter runs with a standard binary encoding you need the FIFO to ensure the proper values.

 

If you use a better code scheme like gray code, where only one bit toggles at each step, you can savely use the shift register method.

 

Generally speaking:

   If more than one bit per clock cycle is subject to change in a bus, you need FIFOs.

 

 

Have a nice synthesis

  Eilert

Message Edited by eilert on 09-18-2009 12:01 PM
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Anonymous
Not applicable
5,424 Views

Hi  Eilert

 

Thank you for your valuable informations....I will try my level best to get the synthesis correct

 

Thanks and regards

Anjo

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jprovidenza
Voyager
Voyager
5,418 Views
Registered: ‎08-30-2007

Anjo -

 

Do you also receive as an input the clock that is creating the 40 bit data?  If so, use that

clock to load the data into a fifo, then use your internal clock to read data from the fifo.

 

There are other trick youcould try if you know that your internal clock is much faster than

the external data rate, but, in  general, the fifo scheme is the safest & cleanest way to grab

the data.

 

If you get the external clock and your internal clock is much faster... Use the external clock

to grab the input data and to toggle a new_data_rdy signal.  Using the faster internal clock,

double synchronize the new_data_rdy signal, then, everytime it toggles, grab the data you latched.

 

Note that metastibility is not the only problem.   The real problem is that with non-related clocks,

you'll miss/meet setup/hold times on some signals and not others.  This may or may not cause

metastability, but it will cause grabbing some data and missing other data until the next cycle.

 

 

Hope this helps!

 

John Providenza

 

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