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Participant
Participant
9,686 Views
Registered: ‎04-04-2016

clock wizard issue (Vivado 2015.4)

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I have a 33Mhz clock input available and my system need to work synchronously at 16MHz. 

My understanding is that this could be achieved instantiating a MMCME2_ADV in my top VHDL architecture; now, since direct instantiationof MMCME2_ADV is complex, I thought to use the clocking wizard IP so I created a bd file, add the ip, customize it, connect to external port and generate"output products". I was expecting one component VHDL file instantiating the IP in the architecture but apparently VIVADO blasted  a 5 levels chinese boxes Verilog hyerarchical behemoth. See picture: 

behemoth.png

I suppose I misunderstood the procedure, can anyone help me back on track?

Thanks

 

 

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Xilinx Employee
Xilinx Employee
18,693 Views
Registered: ‎09-20-2012

Hi @guidopc

 

These additional files came up as you have added the IP to block design, instead add it to the project directly. Open IP catalog, double click on the clocking wizard IP, select "customize IP", select the necessary options and generate the IP.

 

In the IP sources tab, you can find the IP instantiation template, which you can copy and paste in to your RTL and connect the IP pins 

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
18,694 Views
Registered: ‎09-20-2012

Hi @guidopc

 

These additional files came up as you have added the IP to block design, instead add it to the project directly. Open IP catalog, double click on the clocking wizard IP, select "customize IP", select the necessary options and generate the IP.

 

In the IP sources tab, you can find the IP instantiation template, which you can copy and paste in to your RTL and connect the IP pins 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Participant
Participant
9,673 Views
Registered: ‎04-04-2016

Thanks Vemulad,

I followed your hint and now the situation is not so messy. See picture:

Untitled.jpg

But I still don't understand why the system is generating two Verilog files (clk_wiz_0_clk_wiz.v and clk_wiz_0.v) instead of one and if there is a possibility of generating vhdl code instead of verilog.

For some reason my company doesn't permit use of verilog code.

Best regards

 

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Visitor
Visitor
2,791 Views
Registered: ‎07-01-2017

Hi guidopc !

Did you connect VHDL clock wizard to you project ?  If  yes can you share it to others ?

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