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Visitor
7,996 Views
Registered: ‎02-04-2011

## clock

can any one help me how the clock circuit will be for the fpga to detect the rising edge or how the fpga will detect the rising edge of clock
20 Replies
7,993 Views
Registered: ‎10-05-2010

## Re: clock

Assuming your clock is arriving on an input called clock, you would do:

In Verilog:

```always @(posedge clock)
begin
..
end
```

In VHDL:

```process(clock)
begin

if(rising_edge(clock)) then
..
end if;

end process;
```

Internally, clocks are generally applied to the clock inputs of flip-flops.

Visitor
7,991 Views
Registered: ‎02-04-2011

## Re: clock

so flipflop will process the data when there is rising edge right,so how it will be detected
7,987 Views
Registered: ‎10-05-2010

## Re: clock

A D flip flop extends an R-S flip flop to only register the 'D' value when the clock goes high. Following is a diagram showing a D flip flop.

Visitor
7,985 Views
Registered: ‎02-04-2011

## Re: clock

ya fine i got some new thing ,but still i m having doubt ,clock is just a signal, so how fpga will sense logic level '1' and go do some job,ie how fpga knows its the rising edge or the falling edge
7,982 Views
Registered: ‎10-05-2010

## Re: clock

To detect a falling edge, just invert the clock before it goes into the D flip flop and Bob's your uncle.

Visitor
7,980 Views
Registered: ‎02-04-2011

## Re: clock

k can u just give me clock circuit which detects rising edge which is going to fpga
7,978 Views
Registered: ‎10-05-2010

## Re: clock

I've given you the Verilog and VHDL templates for detecting rising edges and a method for building a D flip flop from logic gates that detects rising edges - if these didn't help, what exactly is it that you are after?

Visitor
7,973 Views
Registered: ‎02-04-2011

## Re: clock

o if you have a clock signal with a period of less than 100 ns it will have a better rise time than in my flimsy calculation above, even if it is just a sine wave. Once the signal hit's the voltage margins for '0' and '1' the input driver wil toggle and generate a fine clock edge inside the FPGA, where things go really fast. ;-)

what u say abt this i had founfd in forum only but i m not getting this can u pls explain me
7,968 Views
Registered: ‎10-05-2010

## Re: clock

The text is lacking context, but seems to be referring to the fact that FPGA input pins are digital in nature, and have threshold voltages above and below which a signal is registered as 1 or 0.

Note that the region in between is undefined and your signals have no business spending any time in there. If you're really trying to clock your FPGA from a sine wave, you should use something like a Schmitt trigger or comparator externally to convert them to digital signals first.

Visitor
7,616 Views
Registered: ‎02-04-2011

## Re: clock

everthing is fine can u pls explain me how the d flipflop will operate because when d is 1 the data output is 0,but pulse out 1 i m not getting
Visitor
7,614 Views
Registered: ‎02-04-2011

## Re: clock

can u pls explain the d flipflop circuit
7,614 Views
Registered: ‎10-05-2010

## Re: clock

I'm sorry, but I can not understand the wording of your question.

Are you observing incorrect behaviour from a D flip flop you've built or have instantiated in an FPGA (where? how?) or are you having trouble understanding the D flip flop truth table?

Highlighted
Visitor
7,612 Views
Registered: ‎02-04-2011

## Re: clock

no, i want to know how fpga detects the rising edge,we can right in rtl as u told but internal behaviour how it will be synthesized how the operation works inside fpga
Tags (1)
7,609 Views
Registered: ‎10-05-2010

## Re: clock

The rising edge is detected using a circuit similar to (but considerably more complicated than) the NAND gate construction I posted in message 4. Each slice in a Xilinx FPGA contains several (2 in a Spartan-3, 8 in a Spartan-6) such flip flops. These are present on the silicon. Have you done an elementary digital logic design course? Can you ask a tutor to explain these concepts to you?

For the gory details, read your FPGA's data sheet. In the DS312-3 (v3.8) I have under my pillow to ward off night terrors, it's on page 31 under "Storage Elements".

Visitor
7,606 Views
Registered: ‎02-04-2011

## Re: clock

k thanks for ur reponse good comment
Historian
7,595 Views
Registered: ‎02-25-2008

## Re: clock

@sen_dexcel wrote:
can u pls explain the d flipflop circuit

This is generally taught in sophomore electrical engineering courses. Please revisit your textbooks.

----------------------------Yes, I do this for a living.
Instructor
7,593 Views
Registered: ‎07-21-2009

## Re: clock

@joelby wrote:

A D flip flop extends an R-S flip flop to only register the 'D' value when the clock goes high. Following is a diagram showing a simplified D flip flop.

The diagrammed circuit is a latch, not a flip-flop.  FF is edge-sensitive, latch is level-sensitive.

Seriously, if sen_dexcel can't pick up on the meaning and use of a flip-flop after 17 posts exchanged, a user forum such as this is not a useful venue for teaching sen_dexcel the fundamentals of digital logic systems.  This stuff needs to be learned in person, and in interactive realtime with a live instructor.

Learning how a flip-flop works is not going to be the final and concluding lesson in sen_dexcel's education, right?

-- Bob Elkind

SIGNATURE:

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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7,578 Views
Registered: ‎10-05-2010

## Re: clock

You're right - I've amended the description to indicate that it's a latch (though you know how easy it is to infer a latch).

A complete D FF circuit is too complex to make much sense to the uninitiated, hence the simplification.

Instructor
7,575 Views
Registered: ‎07-21-2009

## Re: clock

...a latch, which is a simplified (level sensitive, rather than edge sensitive) D flip flop.

You're killing me, Joelby!  You're killing me!

Try this diagram, from Wiki.

Or this one (very representative of CMOS and ECL/CML implementations):

-- Bob Elkind

SIGNATURE:

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.