08-29-2011 04:41 AM
08-29-2011 04:52 AM
Assuming your clock is arriving on an input called clock, you would do:
always @(posedge clock) begin .. end
process(clock) begin if(rising_edge(clock)) then .. end if; end process;
Internally, clocks are generally applied to the clock inputs of flip-flops.
08-29-2011 05:18 AM - edited 08-29-2011 04:10 PM
A D flip flop extends an R-S flip flop to only register the 'D' value when the clock goes high. Following is a diagram showing a D flip flop.
08-29-2011 05:31 AM
08-29-2011 05:45 AM
I've given you the Verilog and VHDL templates for detecting rising edges and a method for building a D flip flop from logic gates that detects rising edges - if these didn't help, what exactly is it that you are after?
08-29-2011 05:52 AM
08-29-2011 06:08 AM
The text is lacking context, but seems to be referring to the fact that FPGA input pins are digital in nature, and have threshold voltages above and below which a signal is registered as 1 or 0.
Note that the region in between is undefined and your signals have no business spending any time in there. If you're really trying to clock your FPGA from a sine wave, you should use something like a Schmitt trigger or comparator externally to convert them to digital signals first.
08-29-2011 06:12 AM
08-29-2011 06:15 AM
I'm sorry, but I can not understand the wording of your question.
Are you observing incorrect behaviour from a D flip flop you've built or have instantiated in an FPGA (where? how?) or are you having trouble understanding the D flip flop truth table?
08-29-2011 06:18 AM
08-29-2011 06:27 AM
The rising edge is detected using a circuit similar to (but considerably more complicated than) the NAND gate construction I posted in message 4. Each slice in a Xilinx FPGA contains several (2 in a Spartan-3, 8 in a Spartan-6) such flip flops. These are present on the silicon. Have you done an elementary digital logic design course? Can you ask a tutor to explain these concepts to you?
For the gory details, read your FPGA's data sheet. In the DS312-3 (v3.8) I have under my pillow to ward off night terrors, it's on page 31 under "Storage Elements".
08-29-2011 09:11 AM
can u pls explain the d flipflop circuit
This is generally taught in sophomore electrical engineering courses. Please revisit your textbooks.
08-29-2011 09:26 AM - edited 08-29-2011 09:32 AM
A D flip flop extends an R-S flip flop to only register the 'D' value when the clock goes high. Following is a diagram showing a simplified D flip flop.
The diagrammed circuit is a latch, not a flip-flop. FF is edge-sensitive, latch is level-sensitive.
Seriously, if sen_dexcel can't pick up on the meaning and use of a flip-flop after 17 posts exchanged, a user forum such as this is not a useful venue for teaching sen_dexcel the fundamentals of digital logic systems. This stuff needs to be learned in person, and in interactive realtime with a live instructor.
Learning how a flip-flop works is not going to be the final and concluding lesson in sen_dexcel's education, right?
-- Bob Elkind
08-29-2011 03:55 PM
You're right - I've amended the description to indicate that it's a latch (though you know how easy it is to infer a latch).
A complete D FF circuit is too complex to make much sense to the uninitiated, hence the simplification.
08-29-2011 04:08 PM - edited 08-29-2011 05:24 PM
...a latch, which is a simplified (level sensitive, rather than edge sensitive) D flip flop.
You're killing me, Joelby! You're killing me!
Try this diagram, from Wiki.
Or this one (very representative of CMOS and ECL/CML implementations):
-- Bob Elkind