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Explorer
Explorer
5,667 Views
Registered: ‎08-23-2011

constraining gated clocks in ISE 14.1 ...

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hi,

i have already seen xilinx AR#38099 but i still have issues regarding constraining gated clocks in ise 14.1 using constraints editor -

i have  a simple design as follows -

 

module main (input clk1, input clkg1, input rst, input [3:0] din1, output [3:0] dout1)

 

assign clkg_out1 = clk1 & clkg1; //clk1 is the reference clk and clkg1 is the clk gate enable
always @ (posedge clkg_out1 or negedge rst) begin
     if (!rst) 
         dout1 <= 4'd0;
     else
        dout1 <= din1 + 3'd5;
end
end module
 
i have the proper constraint on clk1 - 
NET "clk1" TNM_NET = clk1;
TIMESPEC TS_clk1 = PERIOD "clk1" 10 ns HIGH 50%; 
 
my issues are as follows -
1) when i synthesize the above design and open the constraint editor, it shows clkg1 as an unconstrained clock (but clkg1 is the gate enable in my design). i even put false path on clkg1 (NET clkg1 TIG), yet this is shown as an unconstrained path. why is the tool showing clkg1 as an unconstrained clock?
 
2) the constraint editor does not show the o/p of the clock gate (clkg_out1) as an unconstrained clock!!! how do i locate this net or inst in the ISE constraints editor in order to constraint it?
 
3) i did try and put a constraint on the clock gate output manually, by looking at the clock gate output in the technology view. i tried the following - 
 
INST "clkg_out11.O" TNM_NET = gated_clk;
TIMESPEC TS_gated_clk = PERIOD "clkg_out11.O" TS_clk1*1;
 
NET "clkg_out1" TNM_NET = gated_clk;
TIMESPEC TS_gated_clk = PERIOD "clkg_out1" TS_clk1*1;
 
when i verify the above using the constraint editor, all the above gave the same issue - Unable to find any TNM group that matches name clkg_out11.O (or clkg_out1). Please fix this problem.
 
what is the best way to constraint a gated clock output?
 
4) if i have a large number of gated clocks in my design (~50), do i need to constraint them manually or is there an automated way for the tool to do it in?
 
please let me know soon ...
 
thanks,
zubin
 
 

 

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1 Solution

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Moderator
Moderator
10,488 Views
Registered: ‎01-16-2013

Re: constraining gated clocks in ISE 14.1 ...

Jump to solution

@zubin_kumar31,

 

  1. when i synthesize the above design and open the constraint editor, it shows clkg1 as an unconstrained clock (but clkg1 is the gate enable in my design). i even put false path on clkg1 (NET clkg1 TIG), yet this is shown as an unconstrained path. why is the tool showing clkg1 as an unconstrained clock?

[Sol] clkg1 is clock input hence it is shown as unconstrained clock in constraint editor.  As there is no TIMESPEC defined on clkg1, it will be shown as unconstrained clock.

 

  1. The constraint editor does not show the o/p of the clock gate (clkg_out1) as an unconstrained clock!!! how do i locate this net or inst in the ISE constraints editor in order to constraint it?
  2. what is the best way to constraint a gated clock output?

 

Sol] clkg_out1 is derived from LUT which is a non-sequential element hence it will not be shown as unconstrained clock.

NOTE:

  1. Such type of clock gating is not supported in FPGA.
  2. The clock constraint won’t get propagated when using a LUT or any combinational circuit.
  3. The recommended way is to use BUFGCE for clock gating in Virtex 5 devices. Please check out Clock Gating for power saving at page number 26 in below UG:

http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

 

  1. if i have a large number of gated clocks in my design (~50), do i need to constraint them manually or is there an automated way for the tool to do it in?

Sol] You have to manually write the constraint for the gated clock.

 

Check out the generalized AR on constraining the gated clock in ISE:

http://www.xilinx.com/support/answers/38099.html

 

Also please check topic “clocking Guidelines” page 205 in below ISE timing user guide which states that Not too use gated clocks.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ug612.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
2 Replies
Moderator
Moderator
10,489 Views
Registered: ‎01-16-2013

Re: constraining gated clocks in ISE 14.1 ...

Jump to solution

@zubin_kumar31,

 

  1. when i synthesize the above design and open the constraint editor, it shows clkg1 as an unconstrained clock (but clkg1 is the gate enable in my design). i even put false path on clkg1 (NET clkg1 TIG), yet this is shown as an unconstrained path. why is the tool showing clkg1 as an unconstrained clock?

[Sol] clkg1 is clock input hence it is shown as unconstrained clock in constraint editor.  As there is no TIMESPEC defined on clkg1, it will be shown as unconstrained clock.

 

  1. The constraint editor does not show the o/p of the clock gate (clkg_out1) as an unconstrained clock!!! how do i locate this net or inst in the ISE constraints editor in order to constraint it?
  2. what is the best way to constraint a gated clock output?

 

Sol] clkg_out1 is derived from LUT which is a non-sequential element hence it will not be shown as unconstrained clock.

NOTE:

  1. Such type of clock gating is not supported in FPGA.
  2. The clock constraint won’t get propagated when using a LUT or any combinational circuit.
  3. The recommended way is to use BUFGCE for clock gating in Virtex 5 devices. Please check out Clock Gating for power saving at page number 26 in below UG:

http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

 

  1. if i have a large number of gated clocks in my design (~50), do i need to constraint them manually or is there an automated way for the tool to do it in?

Sol] You have to manually write the constraint for the gated clock.

 

Check out the generalized AR on constraining the gated clock in ISE:

http://www.xilinx.com/support/answers/38099.html

 

Also please check topic “clocking Guidelines” page 205 in below ISE timing user guide which states that Not too use gated clocks.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ug612.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Moderator
Moderator
5,335 Views
Registered: ‎01-16-2013

Re: constraining gated clocks in ISE 14.1 ...

Jump to solution

@zubin_kumar31

 

I have your SR#10353972 which was filed on the same query with Xilinx technical support but all my emails to your hotmail ID are getting bounced back. 

 

I have sent you a personal message in Xilinx forums. Please check and respond.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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