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Participant
53,207 Views
Registered: ‎07-11-2009

## conversion from binary to integer and vice versa

Hi !

Is it possible to convert the input data in binary form (std_logic_vector) to integer in VHDL?  The converted  integer data is used to perform some fixed point calculations using AccelDSP from xilinx. Once the calculations are made,the output generated from the AccelDSP is integer and my second question is, is it possible to convert back the result into std_logic_vector again?

Milan

6 Replies
Observer
53,198 Views
Registered: ‎05-05-2009

Hi,

to convert std_logic_vector to integer use conv_integer(std_logic_vector_signal).

To convert integer to std_logic_vector use conv_std_logic_vector(integer_signal, num_bits).

num_bits are the number of bits the resulting std_logic_vector signal will have.

for example:

signal sig1 : std_logic_vector(15 downto 0):=X"0123";

signal sig2 : integer range 0 to 65535:=0;

signal sig3 : integer range 0 to 65535:=456;

signal sig4 : std_logic_vector(15 downto 0):=X"0000";

--To convert sig1-->sig2

sig2<=conv_integer(sig1);

--To convert sig3-->sig4

sig4<=conv_std_logic_vector(sig3,16);

regards,

Matthias

Historian
53,180 Views
Registered: ‎02-25-2008

matthias.meurer wrote:

Hi,

to convert std_logic_vector to integer use conv_integer(std_logic_vector_signal).

To convert integer to std_logic_vector use conv_std_logic_vector(integer_signal, num_bits).

num_bits are the number of bits the resulting std_logic_vector signal will have.

for example:

signal sig1 : std_logic_vector(15 downto 0):=X"0123";

signal sig2 : integer range 0 to 65535:=0;

signal sig3 : integer range 0 to 65535:=456;

signal sig4 : std_logic_vector(15 downto 0):=X"0000";

--To convert sig1-->sig2

sig2<=conv_integer(sig1);

--To convert sig3-->sig4

sig4<=conv_std_logic_vector(sig3,16);

regards,

Matthias

Please do not recommend std_logic_arith. It's broken, it's deprecated, and it's been replaced by numeric_std.

----------------------------Yes, I do this for a living.
Historian
53,179 Views
Registered: ‎02-25-2008

maharjanmilan wrote:

Hi !

Is it possible to convert the input data in binary form (std_logic_vector) to integer in VHDL?  The converted  integer data is used to perform some fixed point calculations using AccelDSP from xilinx. Once the calculations are made,the output generated from the AccelDSP is integer and my second question is, is it possible to convert back the result into std_logic_vector again?

Milan

Look up the functions in the numeric_std library. See Ashenden's book for some good help.

Your conversion functions depend on whether the binary value represents a signed or an unsigned number. The numeric_std library adds proper signed and unsigned types.

use numeric_std.all;

.... at the declarative part of the architecture (between the architecture keyword and the begin):

signal foo_slv : std_logic_vector(15 downto 0); -- a 16-bit binary vector

signal foo_us : unsigned(15 downto 0);          -- a 16-bit unsigned vector

signal foo_int : natural range 0 to 65535;      -- a 16-bit natural (non-negative integer)

and in the main body of the architecture:

-- going from SLV to integer:

foo_slv <= X"ABCD";

foo_us  <= unsigned(foo_slv);    -- this is a typecast

foo_int <= to_integer(foo_us);   -- overloaded function

-- going from integer to SLV:

foo_int <= 12345;

foo_slv <= std_logic_vector(to_unsigned(foo_int, foo_slv'length));

-a

----------------------------Yes, I do this for a living.
Teacher
53,150 Views
Registered: ‎07-09-2009

Hi

this is a few pages on a site I regularly print out for people wiht these sort of questions,

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

might be of future help

Participant
53,057 Views
Registered: ‎12-17-2007