08-12-2011 11:53 PM
1. xilinx 10.1
on my board done pin is getting high,but the code i've dumped is not running on the fpga( i even removed clock from my code only given some data(X"555") to outputs) but outputs are not coming instead all l/o pins are showing high.
Thanks in Advance,
08-13-2011 02:29 AM
Try issuing another 12 or CCLK pulses after DONE goes high. In the Spartan-3 Configuration User Guide, this is part of the Startup Sequence.
-- Bob Elkind
08-14-2011 05:59 PM - edited 08-14-2011 06:00 PM
Also check your bitgen settings. If you are configuring from JTAG, the startup clock
will automatically be switched to JTAG by the Impact software. If you have manually set the
startup clock to JTAG and then tried to start up from a PROM or Flash device, then
no number of CCLK pulses will start up the FPGA. Make sure the setting is (default)
Another issue I've seen with Virtex 5, but not Spartan 3, is that when running slave
serial mode and running really fast (V5 configures at 100 MHz), then sometimes
the V5 startup logic will lock up because the DONE pin is sampled while it is still
rising. In that case, slowing down CCLK or driving DONE high, or using the "internal
DONE pipe" will fix the problem.
08-19-2011 04:03 PM
If the done pin is going high then there at least was a clock source, unless something is really haywire. You should post the status register after you try to program from impact (it's another option in impact, like programming or reading idcode). That could be helpful for debug. The done pin being released is part of the startup sequence so make sure you are following the Xilinx requirement to connect a 330 Ohm pull-up resistor on done.
However, I'm not convinced this is a configuration issue, which is why the status register will be good to look at. How do you know your design isn't working correctly? Did you simulate? Does it work correctly in behavioral simulation? What about a timing simulation? Has any design ever worked on this board?