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appalanaidug
Observer
Observer
3,750 Views
Registered: ‎05-31-2010

done pin high but fpga not running

hi all,

 

platform:

 

1. xilinx 10.1

2.xc3s400a

 

problem:

 

 on my board done pin is getting high,but the code i've dumped is not running on the fpga( i even removed clock from my code only given some data(X"555") to outputs) but outputs are not coming instead all l/o pins are showing high. 

 

 

Thanks in Advance,

Naidu.

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3 Replies
eteam00
Professor
Professor
3,748 Views
Registered: ‎07-21-2009

Try issuing another 12 or CCLK pulses after DONE goes high.  In the Spartan-3 Configuration User Guide, this is part of the Startup Sequence.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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gszakacs
Instructor
Instructor
3,740 Views
Registered: ‎08-14-2007

Also check your bitgen settings.  If you are configuring from JTAG, the startup clock

will automatically be switched to JTAG by the Impact software.  If you have manually set the

startup clock to JTAG and then tried to start up from a PROM or Flash device, then

no number of CCLK pulses will start up the FPGA.  Make sure the setting is (default)

CCLK.

 

Another issue I've seen with Virtex 5, but not Spartan 3, is that when running slave

serial mode and running really fast (V5 configures at 100 MHz), then sometimes

the V5 startup logic will lock up because the DONE pin is sampled while it is still

rising.  In that case, slowing down CCLK or driving DONE high, or using the "internal

DONE pipe" will fix the problem.

 

-- Gabor

-- Gabor
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rho88
Observer
Observer
3,717 Views
Registered: ‎06-22-2011

If the done pin is going high then there at least was a clock source, unless something is really haywire.  You should post the status register after you try to program from impact (it's another option in impact, like programming or reading idcode).  That could be helpful for debug.  The done pin being released is part of the startup sequence so make sure you are following the Xilinx requirement to connect a 330 Ohm pull-up resistor on done.

 

However, I'm not convinced this is a configuration issue, which is why the status register will be good to look at.  How do you know your design isn't working correctly?  Did you simulate?  Does it work correctly in behavioral simulation?  What about a timing simulation?   Has any design ever worked on this board?

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