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Highlighted
6,789 Views
Registered: ‎09-14-2010

floating point FIR filter

i want to design floating point FIR filter. it will include a floatin point multiplier obviously. since real numbers arent synthesiable in VHDL what should i do to design a floating point multiplier?

 

i will be grateful for help...

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Instructor
Instructor
6,784 Views
Registered: ‎07-21-2009

Re: floating point FIR filter

If this is your first FPGA or ASIC design, I would recommend a much simpler problem than a floating point multiplier design for your first go.  Work your way up over time -- from simpler items -- to a FP multiplier.

 

If you are an experienced designer, your first task is to define your design requirements for performance, precision, and accuracy.  FP multipliers are not all alike.

 

-- Bob Elkind

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Teacher
Teacher
6,783 Views
Registered: ‎09-09-2010

floating-point arithmetic units

"What should I do to design a floating-point multiplier?"

Buy one. And a floating point adder/subtractor, which in some respects is more complicated. These are seriously complicated things. Remember, Intel got floating-point units wrong twice!


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Professor
Professor
6,777 Views
Registered: ‎08-14-2007

Re: floating-point arithmetic units

Actually multiplication is the easiest part of floating point arithemetic.  Addition is much harder

because it requires normalization.  Multiplication consists of:

 

multiplying the mantissas

adding the exponents

range and error checking

 

I thought there was a synthesizable floating point package for VHDL?

 

-- Gabor

-- Gabor
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Highlighted
Instructor
Instructor
6,773 Views
Registered: ‎07-21-2009

Re: floating-point arithmetic units

Actually multiplication is the easiest part of floating point arithemetic.  Addition is much harder because it requires normalization.

 

  • Both require rounding (which rounding modes?) and post-rounding normalisation.
  • Add/sub requires both unbounded alignment (before add/sub) and normalisation (after add/sub)
  • There are abundant datapath size/speed/routing tradeoffs to be made

If you seek to support the full suite of IEEE-754 "features" and compatibility, your troubles have just begun.  You will be wasting your youth while running regression tests for design verification.

 

Do we have your attention yet?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Teacher
Teacher
6,763 Views
Registered: ‎08-14-2007

Re: floating point FIR filter

Hi,

there's a FloatingPoint Operator available in Coregen that performs a number of Float operations.

Also there's a limited support of Float operations in sysgen from Version 13.4 on.

 

So there shouldn't be the need for designing the operators (Multiply, add, normalize etc) by yourself.

 

While the need for  float numbers in a FIR might be doubted (Do you really need that high dynamic range? Will your design still be fast and small enough? ) it might be interesting to see how things change over time. FPGAs are getting bigger, Tools getting smarter and once VHDL-2008 becomes supported by the synthesis tools with all the cool new packages (float, fixed, numeric_unsigned) will once again improve productivity. If its for better or for worse time will show.

 

So, make your experience with floating point designs, and tell us about your progress and problems.

But please don't complain that you haven't been warned that there's "danger ahead" by the people of this forum.

 

Have a nice synthesis

  Eilert

 

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Highlighted
6,757 Views
Registered: ‎09-14-2010

Re: floating-point arithmetic units

eteam00: you have all my attention . i am not an experiences designer but i have dont small bitts so thaught to work something complicated. this seems not compliated to me in starting but going throught his discussion it looks like i took a wrong step but not a problem . failure is not a problem although i will try my level best to go through it.
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Highlighted
Professor
Professor
6,755 Views
Registered: ‎08-14-2007

Re: floating-point arithmetic units

If you seek to support the full suite of IEEE-754 "features" and compatibility, your troubles have just begun.  You will be wasting your youth while running regression tests for design verification.

 

Actually the original post said nothing about IEEE-754, as well it should not.  Personally I believe that

the IEEE specification is bloated and originally pushed by Intel to sell their floating point hardware, while

a much simpler implementation might have been adequate for software floating point.  In my first job

as an engineer, I wrote some assembly language programs for 8085 micros.  We bought the floating

point library from Intel, which pushed the code size beyond the size of EPROM in the product.  I

went through and took almost half of the code out of the library, including a lot of error checking

and NaN handling that is of no use for embedded systems.  For something as straightforward

as a FIR filter, you don't need the full IEEE-754 (some will argue of course that you don't even need

floating point), just "scaled" numbers.  You can pick the size of the exponent and mantissa to

avoid overflow, and truncate to zero on underflow.  You still need to align and normalise numbers

for addition, but multiplication should result in already normalised results (or zero).  I don't think

that scaled numbers present on overly hard problem even for implementation in an FPGA.

 

-- Gabor

-- Gabor
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Highlighted
6,749 Views
Registered: ‎09-14-2010

Re: floating-point arithmetic units

thanks for such a good insight into the matter

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