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Observer shivanipatel
Observer
7,698 Views
Registered: ‎10-27-2010

generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

Hi All,

 

I want to generate a serial to parallel register in vhdl which will take clock input with 2 ms clock period and generate 8 clock outputs each shifted by one clock pulse w.r.to preceeding clock output with 8 ms clock period each.

 

Looking for the suggestions..

 

Thanx in advance

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9 Replies
Teacher eteam00
Teacher
7,692 Views
Registered: ‎07-21-2009

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

What is the frequency of the clock outputs?  Are all 8 outputs the same frequency?

 

The 8 outputs are all delayed by 0, 2, 4, 6, 8, 10, 12, 14 mS, respectively?

 

- Bob Elkind

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Scholar drjohnsmith
Scholar
7,675 Views
Registered: ‎07-09-2009

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

so how would you code a serial to parallel  shift register 

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Observer shivanipatel
Observer
7,658 Views
Registered: ‎10-27-2010

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

Thanx for the replies........

 

yes the output signal are of same frequencies delayed by one clock pulse(i.e. 4 ms) from the preceding one..

 

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Teacher eteam00
Teacher
7,654 Views
Registered: ‎07-21-2009

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

yes the output signal are of same frequencies delayed by one clock pulse(i.e. 4 ms) from the preceding one..

According to your original post, one clock period is 2mS, not 4mS.  Correct?

What frequency is your clock output?

You will be using 8 output pins for your 8 clocks, correct?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer shivanipatel
Observer
7,647 Views
Registered: ‎10-27-2010

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

Here my input clock signal is of 2ms(500Hz) clock period....
I needed 8 output signals with freq. (input/4=125 Hz(8 ms clock period)).i.e. each pulse width is of 4ms.

By delay of 4ms i mean to say was.......
outtput2 will be delayed from output1 by 4ms(one pulse)...similarly outtput3 will be delayed from output2 by 4ms and so on.....
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Scholar drjohnsmith
Scholar
7,642 Views
Registered: ‎07-09-2009

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

some one once said

 

a picture is worth a 1000 words

 

can you draw and submirt a timing diagram of what you want ?

 

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Observer shivanipatel
Observer
7,639 Views
Registered: ‎10-27-2010

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

::))right said....

 

anyway...i got my output which i wanted.....thanx for replies

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Scholar drjohnsmith
Scholar
7,609 Views
Registered: ‎07-09-2009

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

well done

 

can you post your answer so others in the future can benifit please,

 

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Observer shivanipatel
Observer
7,552 Views
Registered: ‎10-27-2010

Re: generating 8 clock outputs each shifted by one clock pulse w.r.to preceeding pulse

Sure....

 

entity shift is
  port(ck: in std_logic;
       ck_stepin: inout std_logic;
       ck_steps: inout std_logic_vector(7 downto 0);
       ck_out : inout std_logic;
       ck_gt : inout std_logic);
end shift;

 

architecture archi of shift is

-------Input signal freq of the board is 32 MHz depending on which i have choosen the below dividing factor to convert it to 500 Hz------------
  signal ct_500: std_logic_vector(19 downto 0);-----counter
  signal ck_500: std_logic_vector(19 downto 0):= "00000111110011111111";Dividing factor which gives the 500 Hz pulse

  signal wrap: std_logic:= 0;

egin
 
    process (ck)
      begin
         if (ck'event and ck= '1') then
            if (ct_500 = ck_500) then
                     wrap <= not wrap;
                ct_500 <= (OTHERS => '0');
          else
                     ct_500 <= ct_500+ 1;
          end if;

  end process;

 

ck_out <= wrap;

--------this process generates 250 Hz signal(4 ms clock period)------

process (ck)
begin
    if (ck_out'event and ck_out = '1') then
       ck_gt <= not ck_gt;
    end if;
end process;

 

--------this process generates 125 Hz signal(8 ms clock period)------

process (ck)
begin
   if (ck_gt'event and ck_gt = '1') then
       ck_stepin <= not ck_stepin;
   end if;
end process;

-----this process generates the 8 output signals(of 8 ms clock period) each shifted by one clock pulse w.r.to 500 Hz signal----

process (ck)
begin
   if (ck_out'event and ck_out = '1') then
       ck_steps(7 downto 1) <=  ck_steps(6 downto 0);
        ck_steps(0) <= ck_stepin;
    end if;
end process;

end archi;

 

Have a nice day:)

 

 

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