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Explorer
Explorer
3,843 Views
Registered: ‎01-05-2014

help in "if" condition in verilog having arguments 24 bit wide

Hi,

 

Following are the relevant lines of code

"

 reg [5:0] demux_state = 6'b000000; // MJ Reduced from 7 to 6 bits
   reg [23:0] demux_timeout = 23'd0; // MJ Timeout if idle & reset state
 
 always @(posedge clk)
 
demux_timeout <= demux_timeout + 24'd1;
// Timeout after 8 million clock at 100Mhz is 80ms, which should be
// OK for all sensible clock speeds eg 20MHz is 400ms, 200MHz is 40ms
// TODO ought to parameterise, but this should be fine (4800 baud is
// one byte every 2ms approx)
if (demux_timeout & 24'h800000)
begin
demux_state <= 0;
demux_timeout <= 0;
end"
 
The complete code can be found at
 
 
I am unable to understand what the condition "if (demux_timeout & 24'h800000)" evaluates? I read that if condition can have either a value of 1 (true) or 0(false). But in the above example the arguments of the AND operation: "demux_timeout" and "24'h800000" are 24 bit wide so performing bitwise-AND ('&') will result in a 24 bit output so how does the if condition sets to 1 bit 1 or 0?
 
Please help.
 
Thanks and regards.

 
 
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3 Replies
Teacher muzaffer
Teacher
3,823 Views
Registered: ‎03-31-2012

Re: help in "if" condition in verilog having arguments 24 bit wide

The expression passed to if is converted boolean by a non-zero check ie (exp != 0). This has a value of 1 if all bits of the expression are zero and a value of zero if any of the bits are set. It is also similar to a 'reduction or'
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Explorer
Explorer
3,801 Views
Registered: ‎01-05-2014

Re: help in "if" condition in verilog having arguments 24 bit wide

"The expression passed to if is converted boolean by a non-zero check ie (exp != 0). This has a value of 1 if all bits of the expression are zero and a value of zero if any of the bits are set. It is also similar to a 'reduction or'" .

 

I checked in simulation that if demux_timeout is 24'h800000 in a clock pulse then demux_timeout <= 0; is executed the next clock pulse and then onwards demux_timeout gets incremented by 1 until it again becomes 24'h800000 and the process repeats. So demux_timeout behaves as a counter whose last value is 24'h800000 after which it again goes to 0 and repeats counting incrementing by 1 each clock pulse.So the if condition is getting a value of 1 when demux_timeout is 24'h800000 that is the result of the '&' operation in the if condition is 24'h800000 so MSB is set when if is getting a 1 unlike you said that all bits need to be zero for the if expression to get a value of 1

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Teacher muzaffer
Teacher
3,797 Views
Registered: ‎03-31-2012

Re: help in "if" condition in verilog having arguments 24 bit wide

Yeah, the polarity in my answer is inverted. The value is zero if all the bits of the expression are zero and 1 if any of the bits are set. The latter description is correct in the sense that this is the behavior of a 'reduction-or'.
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