06-03-2015 04:32 PM
I'm trying to get introduced to the guts of Vivado and get up to speed on an existing design. It's been several years since I used ISE so I'm hoping I can find a solution here that won't take 3 weeks of back and forth.
I have something that should be extremely simple, which is changing a clock input from single ended (3.3V LVCMOS) to differential (BLVDS_25) as implemented in a 7Z035FBG676.
I've poked through the forums and found the verilog instantiation format on UG768. I am absolutely lost in trying to get the compiler to accept the changes in the constraints (.xdc) and verilog top level source. Unless I'm mistaken it looks like in one case the block design may have overwritten and commented out my changes.
Is there a clear, easy reference for what should be this simple a task?
06-03-2015 09:52 PM - edited 06-03-2015 09:53 PM
As you have mentioned, "I am absolutely lost in trying to get the compiler to accept the changes in the constraints (.xdc) and verilog top level source", are you facing any errors or critical warnings here? It will be helpful to share the design so that we can suggest for alternate workaround.
06-04-2015 03:21 AM
06-04-2015 03:48 PM
The design is huge. putting the whole thing here for evaluation just isn't feasible.
What I am trying to do is change a single ended input clock in to a differential LVDS input clock. I need to use an IBUFDS, and the documentation says the only option for doing that is to instantiate it in the verilog source.
Let's try something smaller then. We have a top level defined in the block diagram window that includes a block of our in house RTL doing MPEG processing and we also have one of the ARM cores connected on the same block diagram page. Apparently when the block diagram engine created the top level wrapper, it set the inputs and outputs in stone and when I try to hand modify the top level it is overwritten to match the existing block diagram.
So... how do I modify the block diagram to add a new external input to our RTL block, and is there a way to make this so it doesn't fight me tooth and nail? Do I have to burn the project down and start fron scratch at the top level every time I want to change an I/O pin?
06-06-2015 12:42 PM - edited 06-06-2015 12:46 PM
If you are trying to do this at BD level, you can use the selectio wizard (add ip, select io wizard) to add an input buffer. On the clock setup use external clock & differential signalling options. This will insert the ibufds cell you need. The you can connect x_p/x_n pins to input and internal clock net to the clk_out output. Then after synthesis, run the constraints wizard which should figure out this is a clock and allow you to attach a create_clock on it.
06-07-2015 08:05 PM
Yes, I've figured out that I can do that, but I'd rather not snowball the top level of my design if I can avoid it. Again, how may I change the ports of an existing top level RTL block in the BD user interface?
06-07-2015 10:53 PM
06-08-2015 02:08 PM
Maybe I need to backtrack again.
I have an existing design that uses the block diagram tool to integrate a large block of in house created RTL with a bunch of IP and one of the ARM cores in an XC7Z035FBG676. I am going to be doing a ton of ongoing development and modification to the design, and I need to understand how to change the ports on our RTL block. If I simply modify the constraints file and/or the top level RTL instantiation wrapper, the changes are overwritten and undone by the BD tool.
In this specific case, yes I can instantiate another IP block and put it between the external pins and my RTL block. That is an unsatisfying band aid and doesn't actually tell me how to solve the problem.
Is there a simple, direct way to override and modify the BD ports at the top level???????
If not, am I going to have to erase this whole project and start over after I've generated a new constraints page with new ports and pinouts?
I have been reading through the tutorials, and frankly any element of how to enter and modify RTL seems extremely sparse.