08-13-2010 02:03 AM
I want to know how can i implement zero crossing detector using VHDL in FPGA. So i want to implement a digital constant fractional discriminator. The firt part provide a bipolar signal was implemented but i want to know how i can implement zero crossing detector in vhdl.
Thank you for your help!
08-13-2010 09:00 AM
For discrete time signal processing, a zero crossing detector consists of one
stage of pipeline delay to detect changes in the sign of the input signal. When
the signal is negative on one clock cycle and positive on the next you have a
rising zero crossing. When positive on one cycle and negative on the next you
have a falling zero crossing. If you need an offset zero crossing reference
as in your diagram you should use subtraction to generate the sign.
08-14-2010 11:43 AM
Hi Gabor. Thank you for your response. If i have understand your idea to implement a detector zero crossing i should be use a pipeline stage delay. So now i will do a research of how i can implement a pipeline stage delay.
Thank you for your help.
08-16-2010 06:25 AM
I searched how i can realize a stage of pipeline delay but i don't now what's is the pipeline delay.
I have some idea of stage of pipeline but i don't know what'is stage of pipeline delay.
If you have some suggestion it's very helpfull for me.
Thank you for response.
PS: Sorry for my bad english!
08-16-2010 06:34 AM - edited 08-16-2010 06:34 AM
Basically a stage of pipeline in a digital circuit is an edge-triggered flip-flop or register. One stage
of delay would be one clock cycle. Pipelines wilth multiple stages are called shift registers. All this
assumes for your application that your data is sampled on each clock cycle. Otherwise your
pipeline delay stage needs to be adjusted such that the register is update once on each sample
period rather than on each system clock cycle. You didn't mention what form of design entry
you are using for this project?
08-17-2010 12:14 AM - edited 08-17-2010 06:27 AM
Hi ! Thank you for your response. The form of my design entry is 12bit.
Another question when you said "If you need an offset zero crossing reference
as in your diagram you should use subtraction to generate the sign" if i have understand i should replace adder by substractor??
Thank you again
08-18-2010 05:19 AM
This represents one type of zero crossing detector. The output of the comparator
would represent the sign bit of your digitized signal. You should note that the logic
in this diagram implements a positive-going zero crossing detector. If you need
to detect both positive and negative crossings you should change the gate to
an exclusive OR gate. Everything in this diagram except the comparator could be
implemented inside the FPGA. Another question is what sort of signal are you detecting
the zero-crossings of? This diagram was made for a case of a simple sine-wave input.
With most real-world signals you may need some filtering before you detect the
zero crossing or you will likely see many zero-crossings due to noise. In the
diagram the clock is shown as 50 MHz. This is likely to be much faster than
the highest frequency of interest in the incoming signal and therefore more
sensitive to noise.
There is one other problem with the circuit. You should normally have one more
flip-flop between the comparator and the zero-crossing detector flip-flop shown
in the diagram. Otherwise the pulses can have very small widths at the output
because the comparator can change at any point during the clock cycle. In a
system with an A/D converter and using the sampling rate as the clock to the
flip-flop you don't have the same issue because the first "flip-flop" is in effect
inside the A/D converter.
08-18-2010 07:04 AM
The design that i want to implement run in 200MHz and not in 50 MHz. Ok i will use XOR gate to have positive and negative zero crossing detector.
Ok now i just implement a digital comparator as i understand.
Thank you for your explanation it's very helpfull.
08-20-2010 12:50 AM
When my signal is positive the comparator generated 1 and when my signal is positive the comparator generated 0.
No i want to detect when the signal cross negative to positive. Now i just implement an Bascule RS and gate xor, that 's right?
Thank you a lot for your contribution!
08-20-2010 06:17 AM
If you only want to detect negative to positive transitions you should implement the
circuit in your previous post, Figure 6. The XOR gate would detect both positive to negative
and negative to positive transitions.
08-22-2010 10:43 PM
Yes you can use this circuit.
And the verilog code is :
always @(posedge clk)
signal_d <= signal_in;
assign trig_out = signal_in ^ (~signal_d);
Be careful about your voltage comparator's output signal range. It must within the FPGA's input voltage range.
09-07-2011 11:23 PM
hello. regarding to this topic, i have excactly the same issues. i want to implement a zero crossing detector in vhdl for inputed signal that look like the picture below. please is there anyone who can give me some clues? the signal is sampled with fs = 44100Hz
09-08-2011 03:46 AM - edited 09-08-2011 04:36 AM
Please start a new thread. In your new thread:
-- Bob Elkind