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bahnan
Participant
Participant
13,496 Views
Registered: ‎04-13-2010

how can i implement zero crossing detector in FPGA?

Hi everybody!

 

I want to know how can i implement zero crossing detector using VHDL in FPGA. So i want to implement a digital constant fractional discriminator. The firt part provide a bipolar signal was implemented but i want to know how i can implement zero crossing detector in vhdl.

 

 

Thank you for your help!

cfd.jpg
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14 Replies
gszakacs
Instructor
Instructor
13,464 Views
Registered: ‎08-14-2007

For discrete time signal processing, a zero crossing detector consists of one

stage of pipeline delay to detect changes in the sign of the input signal.  When

the signal is negative on one clock cycle and positive on the next you have a

rising zero crossing.  When positive on one cycle and negative on the next you

have a falling zero crossing.  If you need an offset zero crossing reference

as in your diagram you should use subtraction to generate the sign.

 

HTH,

Gabor

-- Gabor
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bahnan
Participant
Participant
13,445 Views
Registered: ‎04-13-2010

Hi Gabor. Thank you for your response. If i have understand your idea to implement a detector zero crossing i should be use a pipeline stage delay. So now i will do a research of how i can implement a pipeline stage delay.

 

 

Thank you for your help.

 

Bahnan

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bahnan
Participant
Participant
13,425 Views
Registered: ‎04-13-2010

Hi everybody.

 

I  searched  how i can realize a stage of pipeline delay but i don't now what's is the pipeline delay.

I have some idea of stage of pipeline but i don't know  what'is stage of pipeline delay.

If you have some suggestion it's very helpfull for me.

Thank you for response.

 

Bahnan

 

 

PS: Sorry for my bad english!

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gszakacs
Instructor
Instructor
13,423 Views
Registered: ‎08-14-2007

Basically a stage of pipeline in a digital circuit is an edge-triggered flip-flop or register.  One stage

of delay would be one clock cycle.  Pipelines wilth multiple stages are called shift registers.  All this

assumes for your application that your data is sampled on each clock cycle.  Otherwise your

pipeline delay stage needs to be adjusted such that the register is update once on each sample

period rather than on each system clock cycle.  You didn't mention what form of design entry

you are using for this project?

-- Gabor
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bahnan
Participant
Participant
13,396 Views
Registered: ‎04-13-2010

Hi ! Thank you for your response. The form of my design entry is 12bit.

Another question when you said "If you need an offset zero crossing reference

as in your diagram you should use subtraction to generate the sign"  if i have understand i should  replace adder by substractor??

 

Thank you again

 

Bahnan

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bahnan
Participant
Participant
13,346 Views
Registered: ‎04-13-2010

Hi everybody.

 

I just want to know if i can use this circuit( view attachement) to detect zero crossing ???

zero_crossing_detector.jpg
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gszakacs
Instructor
Instructor
13,340 Views
Registered: ‎08-14-2007

This represents one type of zero crossing detector.  The output of the comparator

would represent the sign bit of your digitized signal.  You should note that the logic

in this diagram implements a positive-going zero crossing detector.  If you need

to detect both positive and negative crossings you should change the gate to

an exclusive OR gate.  Everything in this diagram except the comparator could be

implemented inside the FPGA.  Another question is what sort of signal are you detecting

the zero-crossings of?  This diagram was made for a case of a simple sine-wave input.

With most real-world signals you may need some filtering before you detect the

zero crossing or you will likely see many zero-crossings due to noise.  In the

diagram the clock is shown as 50 MHz.  This is likely to be much faster than

the highest frequency of interest in the incoming signal and therefore more

sensitive to noise.

 

There is one other problem with the circuit.  You should normally have one more

flip-flop between the comparator and the zero-crossing detector flip-flop shown

in the diagram.  Otherwise the pulses can have very small widths at the output

because the comparator can change at any point during the clock cycle.  In a

system with an A/D converter and using the sampling rate as the clock to the

flip-flop you don't have the same issue because the first "flip-flop" is in effect

inside the A/D converter.

 

Regards,

Gabor

-- Gabor
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bahnan
Participant
Participant
13,336 Views
Registered: ‎04-13-2010

Hi Gabor!

 

The design that i want to implement run in 200MHz  and not in 50 MHz. Ok i will use XOR gate to have positive and negative zero crossing detector.

Ok now i just implement a digital comparator as i understand.

 

Thank you for your explanation it's very helpfull.

 

Bahnan

 

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bahnan
Participant
Participant
13,297 Views
Registered: ‎04-13-2010

hi Gabor!

 

I have implemented digital comparator as you can see in this simulation below. I compare juste the MSB of my signal.

 

 

 

comp.jpg
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bahnan
Participant
Participant
7,934 Views
Registered: ‎04-13-2010

Hi!

 

When my signal is positive the comparator generated 1 and when my signal is positive the comparator generated 0.

No i want to detect when the signal cross negative to positive. Now i just implement an Bascule RS and gate  xor, that 's right?

 

Thank you a lot for your contribution!

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gszakacs
Instructor
Instructor
7,926 Views
Registered: ‎08-14-2007

If you only want to detect negative to positive transitions you should implement the

circuit in your previous post, Figure 6.  The XOR gate would detect both positive to negative

and negative to positive transitions.

 

Regards,

Gabor

-- Gabor
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binx
Xilinx Employee
Xilinx Employee
7,906 Views
Registered: ‎09-07-2009

Yes you can use this circuit.

And the verilog code is :

 

=======================================

module zero_detect(clk,signal_in,trig_out);

  input clk,signal_in;

  output trig_out;

  reg signal_d;

 

  always @(posedge clk)

    signal_d <= signal_in;

 

  assign trig_out = signal_in ^ (~signal_d); 

 

endmodule

=======================================

 

Be careful about your voltage comparator's output signal range. It must within the FPGA's input voltage range.

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kunzreii
Visitor
Visitor
7,540 Views
Registered: ‎09-07-2011

hello. regarding to this topic, i have excactly the same issues. i want to implement a zero crossing detector in vhdl for inputed signal that look like the picture below. please is there anyone who can give me some clues? the signal is sampled with fs = 44100Hz

 

regards.

Tags (1)
sinyal.jpg
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eteam00
Professor
Professor
7,534 Views
Registered: ‎07-21-2009

Kunzreil,

 

Please start a new thread.  In your new thread:

 

  • Your waveform display is too small to be useful
  • you should provide an explanation of the waveform (voltage levels, time scale)
  • What are the frequencies of the signal and your system clock?

 

-- Bob Elkind

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