how to achieve cross clock domain design

[conanandai100]

Hi, all. When I work on my project, I find a problem as follow.

My DDR3 app port is 200 MHz and another memory controller is 100 MHz. There is a DMA between the DDR3 and the controller. I once think that I can use 200 MHz for the DMA design. But the interface between DMA and the controller is not that easy to be done. Especially the timing when sending and receive data and cmd.

I've search the forum for the same thread but not found.

Is there any advice?

Thanks.

[conanandai100]

I don't think FIFO can solve the problem as there is not only data but also cmd. 

And the whole design will call for too many FIFOs.

As the DMA has a BRAM for caching, things sounds more complex.

I wonder if I have to unit the system clock into 100 MHz. The only problem is that the controller is written by others, not me.

[awillen]

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I don't think FIFO can solve the problem as there is not only data but also cmd.

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"cmd" ist also just bits and bytes, so where is the problem? You can use several FIFOs crossing the same clock domains, just remember that two words which you push in the same cycle don't necessarily arrive at the same time.

Alternatively, you can clock the 100MHz and the 200MHz circuits from the same source. Is that feasible in your case?

[conanandai100]

Thanks for your reply.

Yes, the cmd is also bytes. I didn't say it clearly. What I worry about is the interface signals. 

For instance, the controller and DMA need to shockhand when sending and receiving cmd. Here comes the problem.

As the clock frequences are different, I has to keep the signal for two cycles from the DMA to the controller. Otherwise, the controller cannot receive it. That's the problem.

Also, when the controller sends a cmd with 100 MHz, and DMA receives it with 200MHz, it seems to get two same data.

I wonder if I describe the problem I met clearly.

Since I use the DCM, 100MHz and the 200MHz circuits are from the same source.

[awillen · Accepted solution]

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Since I use the DCM, 100MHz and the 200MHz circuits are from the same source.

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Excellent, then you don't really have completely asynchronous clock domains. In fact, the 200MHz side can treat the 100MHz signals as if they were in the same domain, with the clock disabled every second cycle.

Use clock enables and you will be fine.

[conanandai100]

Thank you for your quick reply.

I will search for the asynchronous clock domains related topic and see if I can solve the problem by myself.

Anyway, thanks again.